Showing papers on "Channel length modulation published in 2004"

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

Abstract: This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

Analytical drain thermal noise current model valid for deep submicron MOSFETs

Abstract: In this paper, a physics-based MOSFET drain thermal noise current model valid for deep submicron channel lengths was derived and verified with experiments. It is found that the well-known /spl mu/Q/sub inv//L/sup 2/ formula, previously derived for long channels, remains valid for short channels. Carrier heating in the gradual channel region was taken into account implicitly with the form of diffusion noise source and then impedance field method taking velocity saturation effect was used to calculate the external drain thermal noise current. The derived model was verified by experimental noise for devices with channel lengths down to 0.18 /spl mu/m. Excellent agreement between measured and modeled drain thermal noise was obtained for the entire V/sub GS/ and V/sub DS/ bias regions.

On the ballistic transport in nanometer-scaled DG MOSFETs

Abstract: The scattering effects are studied in nanometer-scaled double-gate MOSFET using Monte Carlo simulation. The nonequilibrium transport in the channel is analyzed with the help of the spectroscopy of the number of scatterings experienced by electrons. We show that the number of ballistic electrons at the drain-end, even in terms of flux, is not the only relevant characteristic of ballistic transport. Then, the drive current in the 15-nm-long channel transistor generations should be very close to the value obtained in the ballistic limit even if all electrons are not ballistic. Additionally, most back-scattering events, which deteriorate the on current, take place in the first half of the channel and, in particular, in the first low field region. However, the contribution of the second half of the channel cannot be considered as negligible in any studied case i.e., for a channel length below 25 nm. Furthermore, the contribution of the second half of the channel tends to be more important as the channel length is reduced. So, in ultrashort-channel transistors, it becomes very difficult to extract a region of the channel, which itself determine the drive current I/sub on/.

Partially depleted SOI MOSFETs under uniaxial tensile strain

Abstract: The effects of tensile uniaxial strain on the DC performance of partially-depleted silicon-on-insulator n and p-channel MOSFETs as a function of orientation and gate length are reported. The drain current of the n-MOSFETs increases for both longitudinal and transverse strain orientations with respect to the current flow direction. In the n-MOSFET, longitudinal strain provides greater enhancement than transverse strain. In contrast, for p-MOSFETs, longitudinal strain decreases the current while transverse strain increases the drain current. The magnitude of the fractional change in drain current decreases as gate length is reduced from 20 to 0.35 /spl mu/m. These phenomena are consistent with those of bulk silicon MOSFETs and are shown to be qualitatively correlated with the piezoresistance coefficients of the Si inversion layer. Analysis of the linear drain current versus gate voltage characteristics shows that the threshold voltage is independent of strain while the change in drain current tracks with the change in effective electron and hole mobility. Closer examination shows that as the gate length is reduced from 20 to 0.35 /spl mu/m, the relative increase in low-field electron and hole mobility is constant for transverse strain and generally decreases with gate length for longitudinal strain.

Threshold voltage roll-off compensation using back-gated MOSFET devices for system high-performance and low standby power

Abstract: A method for compensating the threshold voltage roll-off using transistors containing back-gates or body nodes is provided. The method includes designing a semiconductor system or chip having a plurality of transistors with a channel length of Lnom. For the present invention, it is assumed that the channel length of these transistors at the completion of chip manufacturing is Lmax. This enables one to set the off-current to the maximum value of I-offmax which is done by setting the threshold voltage value to Vtmin. The Vtmin for these transistors is obtained during processing by using the proper implant dose. After manufacturing, the transistors are then tested to determine the off-current thereof. Some transistors within the system or chip will have an off-current value that meets a current specification. For those transistor devices, no further compensation is required. For other transistors within the system or chip, the off-current is not within the predetermined specification. For those transistors, threshold voltage roll-off has occurred since they are transistors that have a channel length that is less than nominal. For such short channel transistors, the threshold voltage is low, even lower than Vtmin, and the off-current is high, even higher than I-offmax. Compensation of the short channel transistors is achieved in the present invention by biasing the back-gate or body node to give increased threshold voltage about equal to Vtmin and hence an off-current that meets the predetermined specification, which is about equal to I-offmax.

A surface potential-based compact model of n-MOSFET gate-tunneling current

Abstract: Aggressive scaling of the gate-oxide thickness has made gate-tunneling current an essential aspect of MOSFET modeling. This work presents a novel physics-based compact model of gate current in the n-MOSFET. A simplified version of the Esaki-Tsu formula is developed to calculate the tunneling current density, in which the original integral is approximated to retain the essential physics without sacrificing computational efficiency required in a compact model. The proposed model is surface potential-based in both the channel and source/drain overlap regions. The channel component of the gate current is physically partitioned into the source and drain parts using a symmetrically linearized version of the charge-sheet model. The partition is implemented in analytical form and accounts for the drain bias dependence of the channel component. A small number of adjustable parameters is sufficient to reproduce the experimentally observed bias and geometry dependence of the gate current for several advanced processes.

High frequency power amplifier circuit and electronic component for high frequency power amplifier

Abstract: In a high frequency power amplifier circuit that supplies a bias to an amplifying FET by a current mirror method, scattering of a threshold voltage Vth due to the scattering of the channel impurity concentration of the FET, and a shift of a bias point caused by the scattering of the threshold voltage Vth and a channel length modulation coefficient λ due to a short channel effect are corrected automatically. The scattering of a high frequency power amplifying characteristic can be reduced as a result.

Temperature dependency of MOSFET device characteristics in 4H- and 6H-silicon carbide (SiC)

Abstract: The advantages of silicon carbide (SiC) over silicon are significant for high power and high temperature device applications. An analytical model for a lateral MOSFET that includes the effects of temperature variation in 6H-SiC poly-type has been developed. The model has also been used to study the device behavior in 4H-SiC at high ambient temperature. The model includes the effects of temperature on the threshold voltage, the carrier mobility, the body leakage current, and the drain and source contact region resistances. The MOSFET output characteristics and parameter values have been compared with previously measured experimental data. A good agreement between the analytical model and the experimental data has been observed. 6H-SiC material system provides enhanced device performance compared to 4H-SiC counterpart for lateral MOSFET.

Organic field-effect transistors with nonlithographically defined submicrometer channel length

Abstract: We developed an underetching technique to define submicrometer channel length polymer field-effect transistors. Short-channel effects are avoided by using thin silicon dioxide as gate insulator. The transistors with 1 and 0.74 mum channel length operate at a voltage as low as 5 V with a low inverse subthreshold slope of 0.4-0.5 V/dec, on-off ratio of 10(4), and without short-channel effects. The poly(3-alcylthiophene)'s still suffer from a low mobility and hysteresis does occur, but it is negligible for the drain voltage variation. With our underetching technique also device structures with self-aligned buried gate and channel length below 0.4 mum are fabricated on polymer substrates.

The influence of body effect and threshold voltage reduction on trench MOSFET body diode characteristics

Abstract: This paper presents a comprehensive study of the body diode characteristics of high-channel density trench power MOSFETs using analytic modeling, 2-dimensional numerical simulation, and physical measurements. The results show that, for state-of-the-art trench MOSFETs, the body diode characteristics are strongly influenced by majority carriers in the channel due to gate-controlled third quadrant conduction. This large channel current is shown to be the result of dynamic threshold voltage lowering due to the MOSFET body effect.

Programmable memory cell using charge trapping in a gate oxide

Abstract: An illustrative embodiment of the present invention includes a non-volatile, reprogrammable circuit switch. The circuit switch includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide. According to the teachings of the present invention, the MOSFET is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2).

Collapse of MOSFET drain current after soft breakdown

Abstract: Gate-oxide soft breakdown (SB) can have a severe impact on MOSFET performance even when not producing any large increase of the gate leakage current. The SB effect on the MOSFET characteristics strongly depends on the channel width W: drain saturation current and MOSFET transconductance dramatically drop in transistors with small W after SB. As W increases, the SB effect on the drain current fades. The drain saturation current and transconductance collapse is due to the formation of an oxide defective region around the SB spot, whose area is much larger than the SB conductive path. Similar degradation can be observed even in heavy ion irradiated MOSFETs where localized damaged oxide regions are generated by the impinging ions without producing any increase of gate leakage current.

Method and apparatus for providing a modulation current

Abstract: Techniques are disclosed for providing modulation current that includes output impedance compensation with a feed-forward bandwidth enhancement and pre-distortion modulation to control waveform transition symmetry A feedback circuit senses output node voltage and increases the overdrive voltage of a current source This offsets the loss of current due to channel length modulation and increases the effective output impedance of the source A feed-forward circuit enhances the bandwidth of the impedance compensation feedback loop Waveform transition symmetry is improved by pre-distorting a laser modulation current by introducing an undershoot current on the falling edge of the modulating current

Design considerations for novel device architecture: hetero-material double-gate (HEM-DG) MOSFET with sub-100 nm gate length

Abstract: The paper presents the results of a systematic analytical characterization, supplemented by 2D device simulation, applied to novel device architecture: hetero-material double-gate (HEM-DG) MOSFET with effective channel length down to 30 nm. A new approach to explain the pertinent device physics is presented, which can facilitate device design and technology selection for enhanced performance. Numerical device simulation data, obtained using 2D device simulator: ATLAS, for threshold voltage, drain induced barrier lowering (DIBL) and subthreshold swing (S) were compared to the model to validate the analytical formulation. The comparison of symmetric DG (SDG) MOSFET and HEM-DG MOSFET configurations demonstrated superiority of HEM-DG MOSFET: ideal S and reduced DIBL. Comparison with simulated results reveals excellent quantitative agreement.

High-frequency characterization and modeling of distortion behavior of MOSFETs for RF IC design

Abstract: High frequency (HF) distortion of MOSFETs has been characterized at different frequencies and bias conditions with a single tone measurement system. The results show that a MOSFET has much higher "low frequency limit" (LFL) than a bipolar transistor with similar critical dimensions, implying that the HF distortion characteristics of MOSFETs operating at a frequency lower than LFL is dictated by its low-frequency behavior. This discovery is useful for designers and modelers to validate the distortion of a MOSFET model for RF application. It has also been found that the second harmonic P/sub f2/ reaches to its minimum as f/sub T/ peaks, due to a similar nonlinearity cancellation as in bipolar transistors. Furthermore, the measured data shows fairly constant distortion characteristics over a wide range of drain biases as the device operates in the saturation region. Simulation with a BSIM3v3-based sub-circuit model demonstrates that the distortion behavior of MOSFETs can be well predicted by an RF model if it can accurately describe both dc and ac characteristics with proper parameter extraction. Sensitivity of the distortion on various physical effects, such as the mobility degradation, velocity saturation, channel length modulation, and drain-induced barrier lowering, are also studied to provide insights of the key nonlinearity variation contributors from a practical modeling point of view.

Gate drive method and apparatus for reducing losses in the switching of MOSFETs

Abstract: Usually, in power converters, the load on a MOSFET is inductive, and the current cannot change rapidly. The drain current is the upper limit of the Miller current, so that if the gate current is larger than the drain current, the gate capacitance will continue to discharge and there can be no Miller shelf. If a parallel capacitor is used with a MOSFET, once the drain voltage starts to rise, the load current divides, placing a new lower limit on the Miller current. To drive a MOSFET with a gate current that exceeds the drain current, the circuit impedances have to be very low, suggesting a new geometry and packaging arrangement for the MOSFET and gate drive. A compatible gate turn of circuit is also disclosed.

A methodology to analyze circuit impact of process-related MOSFET geometry

Abstract: Deep sub-wavelength optical imaging distorts the shape of MOSFET channel on silicon due to proximity and refraction. As a result, channel area is no longer rectangular, i.e., represented by the single channel length and width (LxW) for device simulations, but by an L(W) distribution. This distribution would differ across the optical proximity correction (OPC) and photo process windows, possibly exceeding the typical 10% CD variation entitlement. While one can expect that the process-related L(W) would impact MOSFET electrical properties, its circuit consequences have not been addressed in the typical simulation flow. In this work, we examine the impact of non-rectangular channel geometry on the basic MOSFET parameters such as the drive and leakage current. We then create models of the resulting inverter characteristics and of the static noise margin of an SRAM cell. In the process, we show how to simulate MOSFET gate shape for the different OPC and lithography options and identify the channel sections responsible for the parametric variations. Finally, we calculate electrical characteristics of SRAM cell based on the discretized representation of individual MOSFETs, showing how the distortion of channel geometry would degrade cell performance.

Nanoscale SOI MOSFETs: a comparison of two options

Abstract: We have carried out extensive numerical modeling of nanoscale SOI MOSFETs in order to compare two basic options for ultimate scaling. Both devices are double-gate MOSFETs with ultra-thin undoped (intrinsic) channel, and highly doped electrodes; they differ only in the way the channel is connected to the source and drain. Transistors of the first type feature channels connected directly to elevated (‘‘bulk’’) electrodes, while in MOSFETs of the second type the channel has thin doped extensions. Our numerical model of the devices takes into account the two most important factors limiting the device scaling, namely the gate field screening by source and drain, and quantum-mechanical sourceto-drain tunneling along the channel. The results show that the decrease of the gate length L leads to a gradual device performance degradation, including voltage gain reduction, power dissipation increase, and (most importantly) an exponentially growing sensitivity to parameter variations. The degradation is comparable in devices of both types if L of transistors with thin channel extensions is in-between L and the channel length Lc ¼ L þ 2tox (with oxide thickness tox )o f MOSFETs with bulk electrodes. However, the total (‘‘bulk-to-bulk’’) length LBB of the latter devices is always smaller than that of their thin-extension counterparts (at comparable performance), making the transistors with bulk electrodes the most preferable option for ultimate CMOS scaling. 2004 Elsevier Ltd. All rights reserved.

Scaling rules for SOI MOSFETs operating in the fully inverted mode

Abstract: Two-dimensional device simulation was performed on silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect-transistors (MOSFETs) with various gate length L g various top Si layer thickness t Si and various buried oxide (BOX) layer thickness t BOX . As a result, it was found that when t BOX is large, short channel effect (SCE) cannot be suppressed in a fully depleted (FD) MOSFET only by the simple scaling rule maintaining the ratio of L g to top Si layer t Si more than four. It was also found that the scaling rule breaks down more seriously in a fully inverted (FI) MOSFET. It was confirmed that electric field from the drain region penetrates easily into thick BOX layer, which causes drain-induced barrier lowering (DIBL) at the top Si/BOX interface in deep sub-micron gates SOI MOSFETs. Consequently, it was concluded that the DIBL can be suppressed efficiently by reducing t BOX even in a FI MOSFET.

Nanoscale MOSFET with Split-Gate Design for RF/Analog Application

Abstract: Split-gate engineering has been studied to improve metal-oxide-semiconductor-field-effect-transistors (MOSFETs) down to the 45 nm regime, and it is shown that a properly designed split-gate device can improve both frequency performance and intrinsic gain for a wide range of channel lengths due to enhanced carrier transport and reduced short-channel effects. The relative gate length percentage in the split-gate device can optimize device performance based on cut-off frequency, intrinsic gain and threshold voltage considerations. Its output resistance behavior following drain-induced barrier lowering (DIBL) is studied; sidewall spacer width and substrate doping effect on device RF/analog performance are also discussed in this context.

NMOS composite device Vds bootstrappers

Abstract: NMOS composite device Vds bootstrappers that mitigate the effects of decreased power supply rejection and increased channel length modulation in minimum or short channel length devices. The NMOS composite devices have a native or at least a low threshold device over a short channel device, with the gate of the native or low threshold device being controlled responsive to the input or output of the short channel device to clamp the drain—source voltage of the short channel device while holding the short channel device in saturation. In one embodiment, a native device is used, with the gate or the native device being connected to the gate of the short channel device. Other embodiments, including embodiments in the form of source followers having enhanced linearity are disclosed.

One-pin automatic tuning of MOSFET resistors

Abstract: Methods and apparatus for automatic tuning of MOSFET resistors providing accuracy and linearity throughout process and temperature variations. In accordance with the methods, the source and drain of a MOSFET device are biased in a balanced manner around a common mode voltage using a circuit controlling the gate voltage of the MOSFET to set the current through the MOSFET responsive to the value of a resistor. Operating MOSFETs, such as in MOSFET-C filters, with the same device conductivity type, gate bias, substrate voltage and signal common mode voltage provides linear MOSFET resistors, accurately set by a single resistance value. Use of an external resistor provides a single pin setting of MOSFET resistances, that may be independent of temperature and process variations. Various embodiments are disclosed.

Current mirror compensation using channel length modulation

Abstract: A current compensation circuit for use with a current mirror circuit is disclosed. The current mirror circuit has a current path defined by a first programmable current mirror stage driving a first fanout current mirror stage. The first programmable current mirror stage includes at least one transistor with a channel length exhibiting a first channel length modulation factor λ1. The first fanout current mirror stage connects to a supply voltage source. The current compensation circuit comprises a supply voltage current mirror coupled to the supply voltage source and has a current output coupled to the current path. The compensation circuit further includes a second programmable current mirror coupled in series to the supply voltage current mirror and including at least one transistor with a channel length exhibiting a channel length modulation factor λ2. The second channel length modulation factor λ2 is larger than the first channel length modulation factor λ1. As a result, the first programmable current mirror and the second programmable current mirror cooperate to maintain a bias current through the first fanout current mirror stage substantially independent of changes in the supply voltage.

Geometric Effect of Channel on Device Performance in Pentacene Thin-Film Transistor

Abstract: We fabricated pentacene thin film-transistors on a glass substrate with a SiO2 layer via thermal evaporation in ultrahigh vacuum. We investigated the influence of channel length, channel width, and the deposition rate of a pentacene layer on organic thin film transistors (OTFTs) performance. Field-effect mobility of the transistors markedly increased as channel width decreased and channel length increased. The maximum drain current of OTFTs increased as channel length decreased. These observations indicate that the grain boundary scattering of charge carriers in the pentacene layer is a major hurdle in charge conduction, similarly to the observation in poly-Si TFTs. The maximum field-effect mobility was 0.69 cm2/Vs for a device prepared at 0.1 A/s with a 50 µm channel length and a 20 µm channel width. Channel width/length ratio (W/L) as well as the deposition rate of the pentacene layer should be carefully chosen to increase field-effect mobility and maximum drain current in OTFTs.

MOSFET with short channel structure and formation method thereof

Abstract: A MOSFET with a short channel structure and manufacturing processes for the same are described. The MOSFET has a substrate, a channel region, a source/drain region, a gate dielectric layer and a conductive layer. The channel region in the substrate includes a first region and a second region, in which the first region has a first threshold voltage and the second region has a second threshold voltage, respectively. The first threshold voltage is smaller than the second threshold voltage. The first threshold voltage of the first region can also be adjusted to reduce or increase effectively the resistance of the MOSFET when the MOSFET is turned on or off. Additionally, the first region has a shallower junction depth than that of the normal source/drain extension.

Drain-induced barrier lowering effect and its dependence on the channel doping in 4H-SiC MESFETs

Abstract: The drain-induced barrier lowering (DIBL) effect and its dependence on the channel doping concentration in 4H-SiC metal semiconductor field effect transistors (MESFETs) have been studied using the physical drift and diffusion model Our simulation results showed that the high drain voltage typically applied in 4H-SiC power MESFETs could drastically increase the threshold voltage when the ratio of the gate length to channel thickness (L/sub g//a) is less than 3 Larger channel doping concentration has also been found to enhance the DIBL effect, particularly at small L/sub g//a ratio In order to minimize the DIBL effect, the ratio of L/sub g//a should be kept greater than 3 for practical 4H-SiC MESFETs, especially when the channel doping is more than 5/spl times/10/sup 17/ cm/sup -3/

Drain current thermal noise modeling for deep submicron n- and p-channel MOSFETs

Abstract: The drain current thermal noise has been measured and modeled for the short-channel devices fabricated with a standard 0.18 μm CMOS technology. We have derived a physics-based drain current thermal noise model for short-channel MOSFETs, which takes into account the velocity saturation effect and the carrier heating effect in gradual channel region. As a result, it is found that the well-known Q inv / L 2 ––formula, previously derived for long-channel, remains valid for even short-channel. The model excellently explained the carefully measured drain thermal noise for the entire V GS and V DS bias regions, not only in the n-channel, but also in the p-channel MOSFETs. Large excess noise, which was reported earlier in some other groups, was not observed in both the n-channel and the p-channel devices.

Source-drain symmetry in unified regional MOSFET model

Abstract: This letter investigates major sources of asymmetry in a MOSFET compact model by comparing source versus bulk reference in the drain current, effective field, and effective mobility equations. Contrary to the general belief that a regional threshold voltage (V/sub t/)-based model may pose a symmetry problem, we demonstrate that even with the simple source-extrapolated V/sub t/-based model, it can be symmetric if the drain current and the effective transverse field are derived with bulk as the reference, and the lateral-field effective mobility are properly modeled.

Influence of ballistic effects in ultra-small MOSFETs

Abstract: In nanotransistors where the channel length is comparable to the electron mean free path, ballistic transport is of great importance regarding the device performance (Lundstrom and Ren, 2002). In this context, double gate MOSFET (DGMOS) with effective channel length and silicon thickness equal to 25 nm and 10 nm, respectively, has been studied using semi-classical Monte Carlo simulations to investigate the influence of ballistic electrons.

Impact of Radiation-Induced Back-Channel Leakage and Back-Gate Bias on Drain Current Transients of Thin-Gate-Oxide Partially Depleted Silicon-On-Insulator n-channel Metal–Oxide–Semiconductor Field-Effect Transistors

Abstract: In this study, we analyze the impact of back-channel radiation-induced leakage and back-gate bias on switch-off drain current transients of thin-gate-oxide partially depleted (PD) silicon-on-insulator (SOI) n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs). The presence of radiation-induced positive trapped charges in the buried oxide after 60 MeV proton irradiation is found to reduce the "switch-off" transient times for gate voltages above and below the front-gate threshold voltage for body-to-gate electron valence band tunnelling. An increase in steady-state drain current and an increase in the amplitude of weak inversion drain current transients are observed. A similar effect is observed when applying a positive bias to the back-gate, which is found to generate an "irradiation-like" subthreshold leakage. The observed switch-off drain current transient behavior is explained by taking into account an edge parasitic back-channel transient component, which is added to the conventional front-gate drain current transient.