Showing papers on "Channel length modulation published in 2005"

Threshold Voltage Model for Deep-Submicrometer MOSFET's

Abstract: Based on analysis on short-channel effect and drain induced barrier lowering (DIBL) effect, a threshold voltage model for high-k MOSFET's is etablished by introducing a coefficient that interrelates the two effects. Influences of various factors on threshold voltage shift are simulated and investigated, and the optimal range of k values is obtained.

Shielded channel double-gate MOSFET: a novel device for reliable nanoscale CMOS applications

Abstract: In this paper, the unique features exhibited by a novel double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) in which the front gate consists of two side gates to 1) electrically shield the channel region from any drain voltage variation and 2) act as an extremely shallow virtual extension to the source/drain are presented. This structure exhibits significantly reduced short-channel effects (SCEs) when compared with the conventional DG MOSFET. Using two-dimensional (2-D) and two-carrier device simulation, the improvement in device performance focusing on threshold voltage dependence on channel length, electric field in the channel, subthreshold swing, and hot carrier effects, all of which can affect the reliability of complementary metal oxide semiconductor (CMOS) devices, was investigated.

Body-tied triple-gate NMOSFET fabrication using bulk Si wafer

Abstract: We fabricated firstly body-tied triple-gate NMOSFETs that have fin top width of 30 nm, fin bottom width of 61 nm, fin height of 99 nm, and gate length of 116 nm. Fabrication process steps of the devices are compatible with that of conventional bulk planar channel MOSFET technology and explained in detail in this paper. This MOSFET shows excellent transistor characteristics, such as very low subthreshold swing, Drain Induced Barrier Lowering (DIBL) of 24 mV/V, almost no body bias effect, and orders of magnitude lower I SUB / I D than planar channel DRAM cell transistors. By optimizing process further, it is expected that cost effective body-tied triple-gate MOSFETs can be applied to real Integrated Circuits (ICs).

Method and apparatus for mobility enhancement in a semiconductor device

Abstract: A method and apparatus is presented that provides mobility enhancement in the channel region of a transistor. In one embodiment, a channel region (18) is formed over a substrate that is bi-axially stressed. Source (30) and drain (32) regions are formed over the substrate. The source and drain regions provide an additional uni-axial stress to the bi-axially stressed channel region. The uni-axial stress and the bi-axial stress are both compressive for P-channel transistors and both tensile for N-channel transistors. The result is that carrier mobility is enhanced for both short channel and long channel transistors. Both transistor types can be included on the same integrated circuit.

Open drain driver, and a switch comprising the open drain driver

Abstract: An open drain driver (7) selectively switches a MOSFET switch (MN1) which is passively held in the conducting state into the non-conducting state. The MOSFET switch (MN1) switches an AC analogue input signal on a main input terminal (3) to a main output terminal (4) and the gate of the MOSFET switch (MN1) is AC coupled by a capacitor (C1) to the drain thereof. The open drain driver (7) comprises a first MOSFET (MN2) and a second MOSFET (MN3) through which the gate of the MOSFET switch (MN1) is pulled to ground (Vss). The gate of the first MOSFET (MN2) is coupled to the supply voltage (VDD) for maintaining the first MOSFET (MN2) in the open state. A control signal is applied to the gate of the second MOSFET (MN3) for selectively operating the open drain driver (7) in the conducting state for operating the MOSFET switch (MN1) in the non-conducting state. When the second MOSFET (MN3) is in the non-conducting state, the first MOSFET (MN2) remains in the conducting state until the voltage on a coupling node (9) between the first and second MOSFETs (MN2,MN3) equals the difference between its gate voltage and its threshold voltage, at which stage, any over-voltages applied to the gate of the MOSFET switch (MN1) are divided between the first and second MOSFETs (MN2,MN3). A coupling diode (D1) coupling the coupling node (9) to the supply voltage (VDD) clamps the voltage on the coupling node (9) at the supply voltage (VDD) plus the conducting voltage of the diode (D1), in the event of the voltage on the coupling node (9) rising after the first MOSFET (MN2) has gone into the non-conducting state. The coupling node (9) may be capacitively coupled to the supply voltage (VDD) by a coupling capacitor instead of or as well as the diode (D1) for limiting the voltage on the coupling node (9).

Influence of gate bias of MISiC-FET gas sensor device on the sensing properties

Abstract: The influence of gate bias on the gas sensing properties of SiC-based field effect transistors with catalytic gate and a buried short channel has been studied. The drain current–voltage (Id–VD) characteristics of the device reveal non-saturation property, which is a consequence of the short channel design. The drain current is larger in hydrogen ambient than in oxygen ambient at the same drain voltage. The threshold voltage decreases with increasing positive gate bias, and increases with increasing negative gate bias. When a positive bias is applied to the gate, the Id–VD characteristics reveal a tendency to saturate. A positive gate bias increases the drain voltage response to hydrogen, as compared with a negative applied gate bias. However, a positive gate bias decreases the stability of the device signal. A change in the channel resistivity is the main reason for the change in the electrical properties when a positive gate bias is applied. A physical model that explains the influence of the gate bias has been studied, and the behavior of the barrier height in the channel was estimated by using the temperature dependence of the Id–VD characteristics.

Physical Simulation of Drain-Induced Barrier Lowering Effect in SiC MESFETs

Abstract: The drain-induced barrier lowering (DIBL) effect in 4H-SiC MESFETs has been studied using the physical drift and diffusion model. Our simulation results showed that the high drain voltage typically applied in short-channel 4H-SiC MESFETs could substantially reduce the channel barrier and result in large threshold voltage shift. It is also found that the DIBL effect is more dependent on the ratio of the gate length to channel thickness (Lg/a), rather than the channel thickness itself. In order to minimize the DIBL effect, the ratio of Lg/a should be kept greater than 3 for practical 4H-SiC MESFETs.

Diminished Short Channel Effects in Nanoscale Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect-Transistors due to Induced Back-Gate Step Potential

Abstract: In this letter we discuss how the short channel behavior in sub 100 nm channel range can be improved by inducing a step surface potential profile at the back gate of an asymmetrical double gate (DG) silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect-transistor (MOSFET) in which the front gate consists of two materials with different work functions.

Channel width and length dependence in Si nanocrystal memories with ultra-nanoscale channel

Abstract: The use of nanoscale channel MOSFETs as a candidate for future nonvolatile memory is extensively investigated. The device consists of a wire channel MOSFET with nanometer dimensions on which Si nanocrystals (Si-NCs) are deposited. The memory characteristics as a function of the channel widths for different channel lengths are presented. The channel length dimensions are defined between 100-1000 nm by electron beam lithography and the width dimensions are reduced from a few tens of nanometers down to sub-5 nm by wet etching and thermal oxidation processes. It is found that the controllability of the fabrication process is enhanced as the channel length is reduced to 100 nm. Moreover, memory performances are improved with decreasing channel width due to the bottleneck effect. These results show that the Si-NCs memory is highly scalable in terms of the channel size. In the narrowest channel devices, i.e., in the sub-5-nm range, coulomb-blockade oscillations are obtained due to the ultra-small regions formed in the channel. In such devices, a strong enhancement of the retention characteristics has been found as a result of the quantum mechanical narrow channel effect in the ultra-narrow channel.

Realisation of Large Area 3C-SiC MOSFETs

Abstract: Lateral MOSFET devices with varying size from a single unit cell to 3x3 mm2 containing 1980 unit cells have been realised using two basic technologies; lateral trench MOSFET (LTMOS) with epitaxially grown source and drain, and lateral MOSFET with lightly doped drain (LDDMOS) having implanted source and drain regions. The LDDMOS devices had blocking capability of 100 V and the channel mobility in the range of 10 cm2/Vs in {-110} current flow direction and of 5 cm2/Vs in {110} current flow direction. The properties of both fabricated MOSFET types, LTMOS and LDDMOS, are dominated by a high density of interface states of the order of 1×1013 cm-2eV-1. Both the drain current and the leakage current scale linearly with the device size up to the maximum investigated device size of 3x3 mm2. No size limiting defects have been observed contrary to what is often the case in 4H-SiC material.

A new drain voltage enhanced NBTI degradation mechanism [pMOSFETs]

Abstract: Interface state generation and threshold voltage degradation for various channel length devices, stressed at different drain bias conditions, has been studied. It is found that the NBTI (negative bias temperature instability) effect decreases at low drain bias due to decrease in effective gate bias near the drain edge. The subsequent increase in degradation at higher drain stress bias is due to non-uniform generation of interface states and subsequent diffusion of generated hydrogen species along the length of the channel. This effect is more pronounced for short channel devices stressed at high temperatures and high drain bias.

MOSFET temperature sensing

Abstract: A MOSFET has its gate voltage controlled to provide a constant drain current of the MOSFET, for example to limit inrush current for charging a capacitance of a power supply arrangement. A decrease in the gate voltage supplied to the MOSFET, corresponding to an increase in the junction temperature of the MOSFET, by more than a determined amount is detected and used to reduce the gate voltage, and hence the drain current, for example to zero, to prevent heating of the MOSFET beyond a maximum operating temperature.

A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation

Abstract: In this work a continuous analytical model for analog simulation of submicron asymmetrically doped silicon-on-insulator (Sol) nMOSFET using the graded-channel (GC) architecture, valid from weak to strong inversion regimes, is proposed. Analytical models accounting for mobility degradation due to the vertical field, channel length modulation, drain induced barrier lowering and velocity saturation effects have been included in the model formulation. Also the action of parasitic bipolar transistor intrinsic to the SOI MOSFET has been considered. The proposed model considers the highly doped part of the GC transistor acting as a'main' transistor, whose drain voltage is modulated by the remaining part of the channel. Experimental results and two-dimensional simulated data were used to test the model, by comparing the drain current and some important characteristics for analog circuit design, such as the transconductance over the drain current ratio and output conductance, achieving a good agreement in both cases. (c) 2005 Elsevier Ltd. All rights reserved.

Short-Channel Effects in 4H-SiC MOSFETs

Abstract: Short-channel effects in SiC MOSFETs have been investigated. Planar MOSFETs with various channel lengths have been fabricated on p-type 4H-SiC (0001), (000-1) and (11-20) faces.^Short-channel effects such as punchthrough behavior, decrease of threshold voltage and deterioration of subthreshold characteristics are observed. Furthermore, the critical channel lengths below which short-channel effects occur are analyzed as a function of p-body doping and oxide thickness by using device simulation. The critical channel lengths in the fabricated SiC MOSFETs are in agreement with those obtained from the device simulation. The results are also in agreement with the empirical relationship for Si MOSFETs.

Low On-Resistance in Normally-Off 4H-SiC Accumulation MOSFET

Abstract: In our previous paper [1], we simulated an accumulation-mode MOSFET with an epitaxial layer channel (epi-channel) that had a high channel mobility. In this paper, we experimentally show that channel mobility is enhanced by the epi-channel. On varying the thickness of the epi-channel, the channel mobility improved from a few cm2/Vs to 100 cm2/Vs. Finally, we show that the “Normally-off” accumulation MOSFET with a 720 V breakdown voltage has a low on-resistance (10.4 m1cm2) and that the 3 × 3 mm2 accumulation MOSFET operates over 10 A and its on-resistance is 19 m1cm2.

A test circuit for measuring MOSFET threshold voltage mismatch

Abstract: A new test circuit is proposed for evaluating MOSFET threshold voltage mismatch. This test circuit consists of many parallel-connected unit cells, in which two MOSFETs are serially-connected each other and the node between them is connected to common wiring through a switch. The threshold voltage mismatch for the two MOSFETs is derived from the DC currents flowing through this test circuit when the switch being ON and OFF. It is shown that the quantity corresponding to the standard deviation of the threshold voltage is derived from the peak value of the ON/OFF current ratio. Experimental test chips, which include the test circuits having different design channel width, design channel length, MOSFET number and channel conductivity, are developed. The reasonable results are obtained from them.

Ballistic quantum transport in nano-scale Schottky barrier tunnel transistors

Abstract: Nanoscale Schottky barrier tunnel transistors (SBTTs) are investigated by solving the two-dimensional Poisson equation self-consistently with ballistic quantum transport equations. We have analyzed the device characteristics of SBTT by varying the device parameters such as the channel length, tunnel barrier height, and gate insulator dielectric constant. We have found that on-current is almost independent of the channel length while off-current drastically increases as the channel length becomes shorter than around 15 nm. Discussions on avoiding such large off-current are presented, in terms of adjusting the Schottky barrier height and using a gate insulator with high dielectric constant.

Compact Modeling of Threshold Voltage in Double-Gate MOSFET including quantum mechanical and short channel effects

Abstract: A compact model for the threshold voltage in DoubleGate MOSFET is developed. The model takes into account short-channel effects, carrier quantization and temperature dependence of the threshold voltage. We assume a parabolic variation of the potential with the vertical position in the silicon film at threshold. An analytical expression for the surface potential dependence as a function of bias and position in the silicon film is also developed and used for the inversion charge calculation. The model is fully validated by 2D quantum numerical simulation and is used to predict the threshold voltage roll-off in Double-Gate MOSFET with very short channel lengths and thin films. The comparison with measured threshold voltage shows that the model reproduces with an excellent accuracy the experimental data. The model can be directly implemented in a circuit simulator code and used for the simulation of elementary Double-Gate MOSFET based-circuits.

Tri-gated molecular field effect transistor and method of fabricating the same

Abstract: A tri-gated molecular field effect transistor includes a gate electrode formed on a substrate and having grooves in a source region, a drain region and a channel region, and at least one molecule inserted between the source and drain electrodes in the channel region. The effects of the gate voltage on electrons passing through the channel can be maximized, and a variation gain of current supplied between the source and drain electrodes relative to the gate voltage can be greatly increased. Thus, a molecular electronic circuit having high functionality and reliability can be obtained.

Reference voltage generation circuit

Abstract: PROBLEM TO BE SOLVED: To prevent a depression-type MOS transistor, which becomes a reference current source, from being affected by a substrate bias effect and a channel length modulation effect. SOLUTION: A reference voltage generation circuit is provided with; a depression-type NMOS transistor MD1 which works, as a reference current source, without a substrate bias; an enhancement-type NMOS transistor MN1 which is connected to a diode; a bias circuit 1 which supplies bias currents corresponding to voltages, which are inputted to a control input terminal 1B, from bias output terminals 1C and 1D to the drains of the MOS transistors MD1 and MN1; and a differential amplifier 3 which outputs a voltage corresponding to a difference between the drain voltages of the MOS transistor MD1 and MOS transistor MN1 to the control input terminal 1B of the bias circuit 1. The reference voltage generation circuit supplies the MOS transistor MN1 with the same current as the drain current of the MOS transistor MD1 to control both drain voltages so that they may be equal, and outputs, as a reference voltage Vref, a voltage between the gate and source of the MOS transistor MN1. COPYRIGHT: (C)2007,JPO&INPIT

Impact of Thermal Sub-Continuum Effects on Electrical Performance of Silicon-on-Insulator Transistors

Abstract: In this manuscript, the impact of scaling on self-heating of silicon-on-insulator (SOI) transistors is investigated. Effect of temperature dependent phonon-boundary scattering in silicon thin films, which results in reduction in thermal conduction in the channel region, is incorporated into a electro-thermal simulation tool. Results of DC electro-thermal simulations are used to study drain current degradation due to self-heating and to obtain the thermal resistance of SOI devices as a function of gate length and silicon layer thickness. The device thermal resistance is increased by nearly a factor of 3 due to the scaling of gate length from 180nm to 10nm. Self-heating in SOI devices with gate length of 10nm can be responsible for up to 30% reduction in the saturation current and neglecting phonon-boundary scattering in the channel region may underestimate the degradation of drain current due to self-heating by nearly a factor of two.Copyright © 2005 by ASME

Comparison of the scaling characteristics of nanoscale silicon N-channel multiple-gate MOSFETs

Abstract: This paper compares the scaling characteristics of the three leading multi-gate MOSFET designs, namely the finFET, trigate and omega-gate. A commercial numerical device simulator is employed using a common set of material parameters, device physics models and performance metrics. Examined initially are the short channel effects including the subthreshold slope S and drain induced barrier lowering DIBL as the gate length is scaled down to 20 nm. Subsequently investigated and compared are the effects of scaling of the fin body's width and height, the oxide thickness and the channel doping. The results suggest that the omega-gate MOSFET shows the best device scaling characteristics

Quasi-SOI MOSFET: a novel architecture combining the advantages of SOI and bulk devices

Abstract: In this paper, a novel structure named as quasi-SOI MOSFET is proposed, which can combine the advantages of both SOI structure and bulk structure. In the quasi-SOI structure, the source/drain regions are quasi-surrounded with insulator and the channel region is directly connected with the bulk substrate. Short channel effects (SCE), parasitic capacitance and self-heating effects (SHE) can be well alleviated. A method to fabricate the quasi-SOI MOSFET is also put forward and realized by process simulation. Quasi-SOI devices can be realized with a channel formed by epitaxial technology and a buried oxide layer formed by thermal oxidation. Simulation results show good scaling capability and excellent heat dissipation. The drive current and the leakage current can be adjusted by changing the substrate doping for specific applications. Cut-off frequencies as high as 220 GHz for NMOS and 130 GHz for PMOS at 20 nm effective channel length (Leff) can be obtained according to process simulation results.

A compact model of the pinch-off region of 100 nm MOSFETs based on the surface-potential

Abstract: We have developed a model for circuit-simulation which describes the MOSFET region from pinch-off to drain contact based on the surface potential. The model relates the surface-potential increase beyond the pinch-off point to the channel/drain junction profile by applying the Gauss law with the assumption that the lateral field is greater than the vertical one. Explicit equations for the lateral field and the pinch-off length are obtained, which take the potential increase in the drain overlap region into account. The model, as implemented into a circuit simulator, correctly reproduces measured channel conductance and overlap capacitance for 100 nm pocket-implant technologies as a function of bias condition and gate length.

Constant current circuit

Abstract: PROBLEM TO BE SOLVED: To provide a constant current circuit capable of containing an influence of the channel length modulation of an FET composing a current mirror circuit and supplying a relatively stable current SOLUTION: The constant current circuit comprises an input side FET and an output side FET composing a current mirror, and an operational amplifier circuit of which an inverting or non-inverting input terminal is connected to each drain terminal of the input side FET and the output side FET, and is composed so that the output current of the output side FET is supplied against a load COPYRIGHT: (C)2005,JPO&NCIPI

Comparison of the scaling characteristics of nanoscale silicon N-channel multiple-gate MOSFETs

Abstract: This paper compares the scaling characteristics of the three leading multi-gate MOSFET designs, namely the finFET, trigate and omega-gate. A commercial numerical device simulator is employed using a common set of material parameters, device physics models and performance metrics. Examined initially are the short channel effects including the subthreshold slope S and drain induced barrier lowering DIBL as the gate length is scaled down to 20 nm. Subsequently investigated and compared are the effects of scaling of the fin body's width and height, the oxide thickness and the channel doping. The results suggest that the omega-gate MOSFET shows the best device scaling characteristics

An analytical threshold voltage roll-off equation for MOSFET by using effective-doping model

Abstract: This paper presents a new analytical threshold voltage roll-off equation for MOSFET by effective-doping model. The short-channel MOSFET is viewed as distributed MOS capacitors with different effective-doping concentration in series. The 2D scale-length approach is adopted to find the potential distribution and the corresponding effective-doping concentration. The source and drain controlled charges are averaged over the channel depletion region to provide more realistic account of the effective-doping concentration. In addition, the lowering of the required band bending and the widening of the channel depletion are considered. As a result, the sub-exponential dependence of the threshold voltage roll-off on channel length is observed. The two governing factors, channel length and drain voltage, can be decoupled in the limit of a mild short-channel effect.

Simulation of 0.18 micron MOSFET and its characterization

Abstract: The research is focused on the development of 0.18µm channel length of nchannel (NMOS) and p-channel (PMOS) enhancement mode MOSFET. Simulation of the process is carried out using Silvaco Athena to modify theoretical values and obtain more accurate process parameters. Non-ideal effect of a MOSFET design such as short channel effects is investigated. The most common effect that generally occurs in the short channel MOSFETs are channel modulation, drain induced barrier lowering (DIBL), punch-through and hot electron effect. Several advanced method such as lightly-doped drain (LDD), halo implant and retrograde well is applied to reduce the short channel effects. At the device simulation process, the electrical parameter is extracted to investigate the device characteristics. Several design analysis are performed to investigate the effectiveness of the advanced method in order to prevent the varying of threshold voltage or short channel effect of a MOSFET device

Internal voltage generator for semiconductor device

Abstract: Disclosed is an internal voltage generator capable of outputting a constant voltage regardless of change of a supply voltage. The internal voltage generator includes a current mirror unit, drivers and a voltage divider and prevents a channel length modulation phenomenon by changing the structure of the current mirror unit.

Gate-length and drain-voltage dependence of thermal drain noise in advanced metal-oxide-semiconductor-field-effect transistors

Abstract: The high thermal-drain-noise coefficient γ for short-channel metal-oxide-semiconductor-field-effect transistors (MOSFETs) has little to do with hot electrons or velocity saturation, but is determined by the potential gradient along the channel. Consequently, an analytical model for circuit simulation, derived by integration with the surface-potential distribution along the channel, reproduces measured noise characteristics without additional fitting parameters. Furthermore, experimental and theoretical data suggest a fixed relation between the source-drain voltage (Vds) gradients of γ under the saturation condition and the threshold-voltage shift (ΔVth) relative to a long-channel MOSFET.