Showing papers on "Channel length modulation published in 2010"

Sub-100 nm Channel Length Graphene Transistors

Abstract: Here we report high performance sub-100 nm channel length grapheme transistors fabricated using a self-aligned approach. The graphene transistors are fabricated using a highly-doped GaN nanowire as the local gate, with the source and drain electrodes defined through a self-aligned process and the channel length defined by the nanowire size. This fabrication approach allows the preservation of the high carrier mobility in graphene, and ensures nearly perfect alignment between source, drain, and gate electrodes. It therefore affords transistor performance not previously possible. Graphene transistors with 45–100 nm channel lengths have been fabricated with the scaled transconductance exceeding 2 mS/µm, comparable to the best performed high electron mobility transistors with similar channel lengths. Analysis of and the device characteristics gives a transit time of 120–220 fs and the projected intrinsic cutoff transit frequency (fT) reaching 700–1400 GHz. This study demonstrates the exciting potential of graphene based electronics in terahertz electronics.

Controlling Short-channel Effects in Deep Submicron SOI MOSFETs for Improved Reliability: A Review

Abstract: This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation (CLM) and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

Analytical Model of Short-Channel Double-Gate JFETs

Abstract: In this paper, we propose a compact model of the short-channel double-gate (DG) JFETs, which are devices intended for low-power logic applications. In order to make the current equation continuous through all operating conditions from the subthreshold to well above the threshold without nonphysical fitting parameters, mobile carriers in depletion regions are considered. For describing the short-channel behavior, relevant parameters extracted from the 2-D analytical solution of Poisson's equation are used to modify long-channel equations. The field-dependent mobility, velocity saturation, channel-length modulation, and drain-induced barrier lowering are considered in the short-channel analysis. Models for the DG JFET are verified through numerically simulated current-voltage characteristics. Based on the model of the DG JFETs, the advantages of the DG JFETs over single-gate MOSFETs-which may have similar fabrication requirements-with the subthreshold regime are addressed.

Comprehensive Noise Characterization and Modeling for 65-nm MOSFETs for Millimeter-Wave Applications

Abstract: Using an external tuner-based method, this paper demonstrates a complete millimeter-wave noise characterization and modeling up to 60 GHz for 65-nm MOSFETs for the first time. Due to channel length modulation, the channel noise continues to increase and remains the most important noise source in the millimeter-wave band. Our experimental results further show that, with the downscaling of channel length, the gate resistance has more serious impact on the high-frequency noise parameters than the substrate resistance even in the millimeter-wave frequency.

Sub-10nm Multi-Nano-Pillar Type Vertical MOSFET

Abstract: The excellent performance of the 10nm gate Multi-Nano-Pillar type (M-) Vertical MOSFET has been numerically shown for the first time. It is made clear that the M-Vertical MOSFET, in comparison with the conventional Single Pillar type (S-) Vertical MOSFET, has achieved an increased driving current by more than 2 times, a nearly ideal S-factor, and a suppressed cutoff-leakage current by less than 1/60 by suppressing both the short channel effect and the DIBL effect. Moreover, mechanisms of these improvements of the M-Vertical MOSFET are made clear. From all of the above, it is shown that the M-Vertical MOSFET is a key device candidate for future high speed and low power LSI's in the sub-10nm generation.

Channel scaling of hybrid GaN MOS-HEMTs

Abstract: In this paper, we have studied the effect of systematic downscaling of MOS channel length of the performance of the hybrid GaN MOS-HEMT with numerical simulations. The improvement in on-state conduction, together with concomitant short channel effects, such as Drain Induced Barrier Lowering (DIBL) and velocity saturation, is quantitatively evaluated. A specific on-resistance of 2.1 mΩ-cm2 has been projected for a MOS channel length of 0.38 μm. We also have assessed the impact of high-k gate dielectrics, such as Al 2 O 3 . In addition, we have found that adding a thin GaN cap layer on top of AlGaN barrier can help reducing DIBL.

Suppression of DIBL and current-onset voltage variability in intrinsic channel fully depleted SOI MOSFETs

Abstract: Intrinsic channel SOI MOSFETs were fabricated and their variability were compared with conventional bulk MOSFETs. It is found for the first time that, besides V TH variability, both DIBL variabitlity and current-onset voltage variability are well suppressed in the intrinsic channel SOI MOSFETs thanks to non-intentionally doped channel. Reduction of channel doping is essential to reduce the characteristics variability in scaled FETs.

A Computational Study of Dopant-Segregated Schottky Barrier MOSFETs

Abstract: A dopant-segregated Schottky barrier MOSFET is simulated by Monte Carlo method in this paper. The feature that dopant-segregated structure can improve on-current is revealed. The influence of dopant-segregated structure parameters on device performance is investigated, and the guideline for device design optimization is that the dopant-segregated region should overlay the whole Schottky barrier region. Some carrier transport details are also demonstrated here. The maximal velocities at source and drain sides all decrease with the increase of dopant-segregated region length. The maximal velocity at source side shows saturation with the existence of dopant-segregated structure when drain voltage increases while the maximal velocity at drain side shows no saturation.

Nonsaturating Drain Current Characteristic in Short-Channel Amorphous-Silicon Thin-Film Transistors

Abstract: Nonsaturating drain current characteristics are analyzed in terms of the channel length modulation (CLM) and the self-heating effect. According to this analysis, the nonsaturating drain current arises if the effective channel length is sufficiently reduced such that the CLM effect leads to a superlinear increase of the drain current beyond saturation. The extracted CLM parameter was around ?' = 1/15 ?m/V for the samples investigated, and a nonsaturating characteristic was observed in hydrogenated-amorphous-silicon (a-Si:H) thin-film transistors (TFTs) with a channel length of 10 ?m or less. Furthermore, in a bias-temperature-stressed short-channel a-Si:H TFT, which has a laterally nonuniform threshold voltage, the experimental data showed a pronounced nonsaturating current in the reverse output characteristics and a much lower and flatter characteristic in the forwardId-Vds data. The nearly flat forward saturation characteristic is discussed in terms of the cancellation of the CLM effect by the effect from the rising threshold voltage at the pinchoff point as the drain bias increases. The pronounced nonsaturating reverse characteristic is explained in terms of the compounding effects of the rising CLM current and the rising current due to the falling threshold voltage of the pinchoff point. We also discuss a split-channel design to suppress the nonsaturating drain currents in a-Si:H TFTs.

Parameter Extraction of Short-Channel a-Si:H TFT Including Self-Heating Effect and Drain Current Nonsaturation

Abstract: We present an extraction procedure of the above-threshold parameters of a modified level-15 model of hydrogenated amorphous-silicon thin-film transistors (a-Si:H TFTs). This procedure is useful for model parameter extraction for short-channel devices, including the self-heating effect (SHE) and the nonsaturating drain current effect via the channel length modulation (CLM). The drain current formula of the AIM-Spice level-15 model was modified to include the nonsaturating drain current and SHE in the model. This procedure is also useful for devices in which the source-drain contact resistance Rsd is comparable to, or greater than, the channel resistance, which is common in short-channel a-Si:H TFTs with a channel length of 10 ?m or less. We propose a modified integral function method for the extraction of contact resistance and threshold voltage. This method includes features of the ratio method and the integral function method. Using this modified integral function method, we extract both the threshold voltage Vt and the series contact resistance Rsd at the very beginning of the extraction process. When simulated data were used for extraction, Vt and Rsd extracted by our proposed method agreed with the true parameter values better than the parameters extracted by the integral function method or the ratio method. For a short-channel device with a significant SHE, the field-effect mobility ? FE parameters were separately extracted for the linear and saturation regions, because ?FE was higher in the saturation region than that in the linear region, which is probably caused by the SHE-induced rise of channel temperature. The calculated I-V characteristics based on the extracted parameters fit the experimental data well in both the short- and long-channel devices. This suggests that the modified drain current model including the SHE and the nonsaturating drain current is valid; the proposed parameter extraction procedure is valid and may be implemented in the circuit simulator, such as AIM-SPICE, with some further improvement in the field-effect mobility formula when SHE is present.

Analytical current equation for short channel SOI multigate FETs including 3D effects

Abstract: Current flow in short-channel multigate FETs is strongly influenced by 2D or even 3D effects. In subthreshold operation the channel current is located in the device center, whereas above threshold the channel moves to the silicon-to-oxide interface. This movement of the most leaky path can result in an abnormal behavior in the transconductance. In this paper an analytical current equation for lightly doped devices is proposed which takes into account these effects. The leakage current is calculated from a three-dimensional solution of the electrostatic potential at the barrier within the channel. For the current above threshold, which is located at the channel surface, a bulk MOS model is superposed. The final current equation takes into account short-channel effects as threshold voltage shift, drain-induced barrier lowering, subthreshold slope degradation and the movement of the most leaky path within the channel cross section. The model has been benchmarked by numerical results and is in good agreement down to a channel length of 30 nm.

Hole-Mobility and Drive-Current Enhancement in Ge-Rich Strained Silicon-Germanium Wire Tri-Gate Metal-Oxide-Semiconductor Field-Effect Transistors with Nickel-Germanosilicide Metal Source and Drain

Abstract: on such Ge-rich non-planar channels. 9) In this letter, we demonstrate a fabrication process and high hole mobility characteristic of uniaxially strained SiGe-on-insulator (SGOI) channel tri-gate MOSFET with Ge fraction x of 0.65 formed by two-step Ge condensation. The current drive of a uniaxially strained SGOI channel tri-gate MOSFET, which has a nickel-germanosilicide (NiSiGe) metal S/D structure with gate length (Lg) of 50 nm and wire width (Wwire) of 25 nm, was also investigated and compared with that of SOI channel tri-gate MOSFETs. Sufficiently high mobility and higher current drive were obtained in the SGOI channel tri-gate FETs than those of the SOI channel tri-gate MOSFET, as well as high immunity to the short-channel effects.

Capacitively coupled switched current source

Abstract: In the preferred embodiment, a current source is switchable between two precisely defined output currents. A terminal of a coupling capacitor is coupled to the gate of an output MOSFET. The other terminal of the capacitor is switched between two reference voltages to toggle the MOSFET to output the selected one of the two currents. A switchable bias voltage source is coupled to the gate only during the on state of the MOSFET to set the gate voltage of the MOSFET. The current output of the current source is quickly and accurately changed. A reference MOSFET is not directly coupled to the output MOSFET, so there are no slow settling components coupled to the gate of the output MOSFET.

Threshold Voltage Dependence on Bias for FinFET using Analytical Potential Model

Abstract: This paper has presented the dependence of the threshold voltage on back gate bias and drain voltage for FinFET. The FinFET has three gates such as the front gate, side and back gate. Threshold voltage is defined as the front gate bias when drain current is 1 micro ampere as the onset of the turn-on condition. In this paper threshold voltage is investigated into the analytical potential model derived from three dimensional Poisson"s equation with the variation of the back gate bias and drain voltage. The threshold voltage of a transistor is one of the key parameters in the design of CMOS circuits. The threshold voltage, which described the degree of short channel effects, has been extensively investigated. As known from the down scaling rules, the threshold voltage has been presented in the case that drain voltage is the 1.0V above, which is set as the maximum supply voltage, and the drain induced barrier lowing(DIBL), drain bias dependent threshold voltage, is obtained using this model.

Sub-threshold reference source compensated by adopting electric resistance temperature

Abstract: The invention discloses a sub-threshold reference source compensated by adopting electric resistance temperature, which belongs to a range of power supply temperature compensating circuits. The sub-threshold reference source adopts positive temperature coefficient compensating circuit and temperature compensating reference voltage source technology of electric resistance, and consists of three parts comprising a peak current mirror, a negative temperature coefficient current generating circuit and a reference voltage output circuit. A sub-threshold reference circuit for generating constant reference voltage output by using the positive temperature coefficient of the electric resistance and the negative temperature coefficient of the current on a resistor can overcome the influence that the output voltage brought by channel length modulation effect is changed by the fluctuation of power supply voltage to a certain degree; and the sub-threshold reference source has a simple structure and low power consumption, can be applied to an analog integrated circuit with low-power consumption design, and can be broadly applied to a reference voltage source circuit required by a low-power consumption analog and digital-analog mixed circuit for generating low temperature coefficients.

Fabrication of Highly Scaled Silicon Nanowire Gate-All-Around Metal–Oxide–Semiconductor Field Effect Transistors by Using Self-Aligned Local-Channel V-gate by Optical Lithography Process

Abstract: The silicon nanowire gate-all-around (GAA) metal–oxide–semiconductor field effect transistors (MOSFETs) have been fabricated by using inverted sidewall spacers to scale the gate length. The patterning strategy of inverted sidewall spacers is based on the self-aligned local-channel V-shaped gate electrode (V-gate) by optical lithography (SALVO) process. Through this technique, we have obtained an aggressively scaled gate length down to 10 nm regime. In addition, the silicon nanowire structure with diameter of about 10 nm has been successfully formed by reducing of the local channel. In the fabricated device, we have confirmed that it has excellent device characteristics in terms of the sub-threshold swing (SS), drain induced barrier lowering (DIBL), and low level of off-state leakage current in spite of the short-channel effect (SCE).

The dependence of saturation velocity on temperature, inversion charge and electric field in a nanoscale MOSFET

Abstract: The intrinsic velocity is shown to be the ultimate limit to the saturation velocity in a very high electric field. The unidirectional intrinsic velocity arises from the fact that randomly oriented velocity vectors in zero electric field are streamlined and become unidirectional giving the ultimate drift velocity that is limited by the collision-free (ballistic) intrinsic velocity. In the nondegenerate regime, the intrinsic velocity is the thermal velocity that is a function of temperature and does not sensitively depend on the carrier concentration. In the degenerate regime, the intrinsic velocity is the Fermi velocity that is a function of carrier concentration and independent of temperature. The presence of a quantum emission lowers the saturation velocity. The drain carrier velocity is revealed to be smaller than the saturation velocity due to the presence of the finite electric field at the drain of a MOSFET. The popular channel pinchoff assumption is revealed not to be valid for either a long or short channel. Channel conduction beyond pinchoff enhances due to increase in the drain velocity as a result of enhanced drain electric field as drain voltage is increased, giving a realistic description of the channel length modulation without using any artificial parameters. The velocity so obtained is considered in modeling the currentvoltage characteristics of a MOSFET channel in the inversion regime and excellent agreement is obtained with experimental results on an 80-nm channel.

A 65nm CMOS low-power, low-voltage bandgap reference with using self-biased composite cascode opamp

Abstract: In this paper, we present a low-voltage low-power CMOS bandgap voltage reference (BVR) based on the self-cascode self-biased op-amp. The current mirror mismatch error resulting from the channel length modulation (CLM) effect has also been compensated by using composite transistors. This proposed circuit, implemented in 65nm IBM CMOS process, which generates a reference of 364mV from a power supply of the 1.2V and consumed the 28 μW at room temperature. The power supply rejection ratio is greater than 60 dB for frequency below 10 kHz. The proposed bandgap achieves a temperature coefficient(TC) of 4.7ppm/°C without trimming for the temperature range(TR) from 0°C to 100°C and the 0.75mV/V of ±10% supply voltage variations.

Effect of Drain Bias Stress on Stability of Nanocrystalline Silicon Thin Film Transistors with Various Channel Lengths

Abstract: We report the electrical stability of bottom-gate nanocrystalline silicon (nc-Si) thin film transistors (TFTs) with various channel lengths under drain bias stress for the first time. As the bias stress at the drain terminal increases at a fixed gate bias, the threshold voltage (VTH) shift of the nc-Si TFTs decreases significantly. Under the drain bias stress, the VTH shift decreases with channel length. The smaller VTH shift was analyzed on the basis of the concentration of the channel charge. A high drain bias reduces the carrier concentration near the drain terminal. Also, the ratio of the depleted charges to total charges increases with decreasing channel length due to the drain bias. Thus, a short-channel TFT has a smaller normalized channel charge than a long-channel TFT. A low carrier concentration induces a small number of defect states; thus the VTH shift of a short-channel TFT is smaller than that of a long-channel TFT.

Scale-Invariant Drain Current in Nano-FETs

Abstract: Starting from a three-dimensional transport model in the Landauer-Buttiker formalism we derive a scale-invariant expression for the drain current in a nano-transistor. Apart from dimensionless external parameters representing temperature, gate-, and drain voltage the normalized drain current depends on two dimensionless transistor parameters which are the characteristic length l and -width w of the electron channel. The latter quantities are the physical length and -width of the channel in units of the scaling length  = ~(2mF )􀀀1=2. Here F is the Fermi energy in the source contact and m is the e ective mass in the electron channel. In the limit of wide transistors and low temperatures we evaluate the scale-invariant ID􀀀VD characteristics as a function of the characteristic length. In the strong barrier regime, i. e. for l & 20 long-channel behavior is found. At weaker barriers source-drain tunneling leads to increasingly signi cant deviations from the long-channel behavior. We compare with experimental results.

Simultaneous enlargement of SRAM read/write noise margin by controlling virtual ground lines

Abstract: The SRAM operating margin in 65nm technology is analyzed. The peak characteristic in the read margin versus the supply voltage was found to be caused by the channel length modulation effect. Controlling the memory cell virtual ground line proved to be effective in enlarging the operating margin simultaneously in the read and the write operations. A simple optimum circuit which does not require any dynamic voltage control is proposed, realizing an improvement in the operating margin comparable to conventional circuits requiring dynamic voltage control.

The Effect of Gate Length on SOI-MOSFETs Operation

Abstract: The effect of gate length on the operation of silicon-on-insulator (SOI) MOSFET structure with a layer of buried silicon oxide added to isolate the device body has been simulated. Three transistors with gate lengths of 100, 200 and 500 nm are simulated. Simulations show that with a fixed channel length, when the gate length is increased, the output drain current characteristics slope is increased, and therefore the transistor transconductance increases. Moreover, with increasing the gate length, the effect of the drain voltage on the drain current is reduced, which results in the reduced drain induced barrier lowering.

Unified drain current model for independently driven double gate MOSFETs

Abstract: A generic surface potential based current voltage (I–V) model for heavily doped asymmetric Double Gate MOSFET is presented. The model is derived from the 1-D Poisson equation with all the charge terms included and the channel potential is solved for the asymmetric operation of DG MOSFET based on the Newton Raphson Iterative method. A non charge sheet based drain current model based on the Pao-Sah's double integral method is formulated in terms of front and back gate surface potentials at the source and drain end. The model is able to clearly show the dependence of the front and back surface potentials and the drain current on the terminal voltages, gate oxide thicknesses, channel doping concentrations and the Silicon body thickness and a good agreement is observed with the 2-D numerical simulation results.

Accurate modelling of organic thin film transistors for analogue circuit simulation

Abstract: Motivation: Electronics based on organic thin-film transistors (OTFTs) enables a variety of attractive applications like active matrix displays, flexible sensor systems and, at a longer timescale, printable item-level RFID tags. As analogue circuit applications of OTFTs are being extensively researched, accurate OTFT models suitable for the simulation of these circuits become increasingly more relevant and urgent. In this work we propose a physically-based, analytical model for OTFTs, which takes into account the influence of both tail and deep localized states. The model is symmetric, considers channel modulation, and provides good accuracy both in sub-threshold and above-threshold regime. It also preserves the continuity of the small-signal parameters, as it is required for analogue simulations. Model, results and discussion: Charge transport in organic semiconductors is usually explained by means of the variable range hopping (VRH) theory, i.e., thermally activated tunnelling of carriers between localized states. From a percolation model of hopping between localized states, Vissenberg and Matters [1] developed an analytic expression of field-effect mobility used to describe transport in OTFTs. Their model is based on the assumption of an exponential DOS. From the direct determination of the DOS by high lateral resolution Kelvin probe measurements [2], it was shown that the ‘’real’’ DOS is well fitted by a Gaussian function in tail states and an exponential function in deep states. Therefore the Vissenberg and Matters work is a very good approximation of the Gaussian DOS only in tail states [3] whereas it neglects deep states. Based on these experimental evidences, we consider the influence of both tail and deep states on the OTFT current. We show that the former are important at high gate voltages when the transistor works in strong accumulation regime and the latter are relevant at low VGS, both in saturation and in sub-threshold regime (see Fig. 1). Channel length modulation is also accounted for in the model, ensuring both current and output-resistance continuity at the pinch-off voltage: this is very important when the model is used in a CAD environment and for analogue design purposes. In Figs. 1, 2 the proposed model (red continuous line) is compared with experimental data: accuracy is good both below- and above- threshold. The model is fully symmetrical and can be easily extended to take into account contact resistance effects. The model parameters are extracted in a simple and direct way from the experimental measurements (without any optimization method) using the standard procedure described in [4]. From measurement in biasing conditions where the drain current is dominated by deep-states, one can determine the flat-band voltage VFB, the conductivity sd and the DOS characteristic temperature Td. It is worth noting that the flat-band condition is unambiguously determined from the deep-states current and, contrary to [5], no other threshold voltage needs to be introduced. Measurements where ID is dominated by tail-states current give st and Tt. Apart from geometric parameters, the model requires only five physical parameters related to the material properties.

Low-FOM planar MOSFET

Abstract: Low FOM (Figure-of-merit) planar MOSFET is presented in this paper. The p-base of the developed MOSFET is formed by self-aligned ion implanted. Only four masks is used to fabrication while the performance of the developed MOSFET is better than the present conventional MOSFET. The optimized 20V rated MOSFET exhibits about 7.8mΩ·mm2 specific on-resistance, 1.2nC·mm2 and 3.4 nC·mm2 gate-drain charge and gate charge respectively. There is a reduction of 57% in the Figure of Merit.

Estimation of surface potential variation in short channel MOSFET by solving 2D Poisson's equation

Abstract: Advances in technology leads to dramatic lowering of MOSFET channel length. However short channel effects (SCE) degrade device performance and put a limit to scaling down of device dimensions. Drain Induced Barrier Lowering (DIBL) is such an effect where threshold voltage rolls off and sub-threshold current increases significantly. Study of the surface potential is important for understanding DIBL. In this paper we propose a numerical model to calculate the variation in surface potential by solving the 2-D Poisson's equation, starting from a more accurate expression for the charge distribution. The results agree with the expected trend.

Analytical Study of Short Channel Effects in Fully Depleted Double Gate and Cylindrical Gate Mosfets

Abstract: The present analysis proposes a comparative study between two methods to solve 2D poisson’s equation making in evidence short channel effects SCE in double-gate (DG) MOSFET and cylindrical-gate (CG) MOSFET. We are interesting in particular to the characteristic length/natural length λ that is a key parameter governing the improved short channel effects.

Modeling fluctuations in the threshold voltage and ON-current and threshold voltage fluctuation due to random telegraph noise

Abstract: We investigate the influence of two traps in close proximity within one nanometer located at the semiconductor/oxide interface (positioned in the middle of the gate width and moved from the source end to the drain end of the channel) on the threshold voltage and the ON-current variation. We find that when one of the traps is located at the source end of the channel, the threshold voltage and the magnitude of the drain current are dominated by the potential barrier created by the negatively charged trap. When the trap is positioned at the drain-end of the channel, the barrier effect is smaller and screening (for small drain bias) and the absence of screening (at large drain bias due to the presence of the pinch-off region) determine whether current will be degraded or not.