Showing papers on "Channel length modulation published in 2012"

Channel Length Scaling of MoS2 MOSFETs

Abstract: In this article, we investigate electrical transport properties in ultrathin body (UTB) MoS2 two-dimensional (2D) crystals with channel lengths ranging from 2 μm down to 50 nm. We compare the short channel behavior of sets of MOSFETs with various channel thickness, and reveal the superior immunity to short channel effects of MoS2 transistors. We observe no obvious short channel effects on the device with 100 nm channel length (Lch) fabricated on a 5 nm thick MoS2 2D crystal even when using 300 nm thick SiO2 as gate dielectric, and has a current on/off ratio up to ∼109. We also observe the on-current saturation at short channel devices with continuous scaling due to the carrier velocity saturation. Also, we reveal the performance limit of short channel MoS2 transistors is dominated by the large contact resistance from the Schottky barrier between Ni and MoS2 interface, where a fully transparent contact is needed to achieve a high-performance short channel device.

A physics based compact model of I–V and C–V characteristics in AlGaN/GaN HEMT devices

Abstract: In this paper we present a physics-based compact model for drain current I d and intrinsic gate–drain and gate–source capacitances C GS and C GD in AlGaN/GaN high electron mobility transistors. An analytical expression for the 2-DEG charge density n s , valid in all the regions of device operation is developed and applied to derive current and capacitances. The drain current model includes important physical effects like velocity saturation, channel length modulation, short channel effect, mobility degradation effect, and self-heating. The expression for n s is used to derive a model for C GS and C GD applicable in all the regions of device operation. The parameters introduced in the model have a clear link to the physical effects facilitating easy extraction of parameter values. The model is in excellent agreement with experimental data for both drain current and capacitances over a typical range of applied voltages and device geometries.

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

Abstract: In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX.

High-Frequency Performance of Self-Aligned Gate-Last Surface Channel $\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ MOSFET

Abstract: We have developed a self-aligned Lg = 55 nm In0.53Ga0.47As MOSFET incorporating metal-organic chemical vapor deposition regrown n++ In0.53Ga0.47As source and drain regions, which enables a record low on-resistance of 199 Ωμm. The regrowth process includes an InP support layer, which is later removed selectively to the n++ contact layer. This process forms a high-frequency compatible device using a low-complexity fabrication scheme. We report on high-frequency measurements showing fmax of 292 GHz and ft of 244 GHz. These results are accompanied by modeling of the device, which accounts for the frequency response of gate oxide border traps and impact ionization phenomenon found in narrow band gap FETs. The device also shows a high drive current of 2.0 mA/μm and a high extrinsic transconductance of 1.9 mS/μm. These excellent properties are attributed to the use of a gate-last process, which does not include high temperature or dry-etch processes.

Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs

Abstract: An analytical compact drain current model for undoped (or lightly doped) short-channel triple-gate fin-shaped field-effect transistors (finFETs) is presented, taking into account quantum-mechanical and short-channel effects such as threshold-voltage shifts, drain-induced barrier lowering, and subthreshold slope degradation. In the saturation region, the effects of series resistance, surface roughness scattering, channel length modulation, and saturation velocity were also considered. The proposed model has been validated by comparing the transfer and output characteristics with device simulations and with experimental results. The good accuracy and the symmetry of the model make it suitable for implementation in circuit simulation tools.

Static Performance of 20 A, 1200 V 4H-SiC Power MOSFETs at Temperatures of −187°C to 300°C

Abstract: Silicon carbide (4H-SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) have been attracting tremendous attention for high-power applications at a wide range of operating temperatures, owing to their normally-off characteristics, high-speed switching operation, avalanche capability, and low on-resistance. To optimize performance of 4H-SiC MOSFETs for various applications at different temperatures, it is important to understand the mechanisms of temperature dependence of the key parameters, such as on-resistance, threshold voltage, and metal–oxide–semiconductor (MOS) channel mobility. We report on the temperature dependence of the on-resistance of 20 A, 1200 V 4H-SiC power MOSFETs for temperatures ranging from −187°C to 300°C. The MOSFET showed normally-off characteristics throughout the entire experimental temperature range. Different temperature dependences of the total on-resistance in different temperature regimes have been observed. Due to the poor MOS channel mobility and the low free carrier concentration in the inversion channel of the 4H-SiC MOSFET, the MOS channel resistance is the dominant part of the total on-resistance. This was also found to be true in a 4H-SiC long-channel lateral MOSFET.

Scalability of Extremely Thin SOI (ETSOI) MOSFETs to Sub-20-nm Gate Length

Abstract: We report high-performance extremely thin SOI MOSFETs fabricated with a channel thickness down to 3.5 nm, sub-20-nm gate length, and contacted gate pitch of 100 nm. At an effective channel length of 18 nm, a drain-induced barrier lowering of 100 mV is achieved by either thinning the channel to 3.5 nm or by applying a reverse back-gate bias to 6-nm channel MOSFETs. Moreover, minimal increase in series resistance is seen when the channel is scaled to 3.5 nm, resulting in no performance degradation with SOI thickness scaling.

Two-Dimensional Analytical Drain Current Model for Double-Gate MOSFET Incorporating Dielectric Pocket

Abstract: In this paper, a dielectric-pocket double-gate MOSFET is described for low-voltage low-power applications. A complete drain current model has been developed including the channel length modulation effect. The analytical results have been validated by comparing them with the simulation results using the ATLAS 3-D device simulator. This paper analyzes the impact of dielectric pillars on large-signal performance metrics in terms of linearity and digital performance. Due to high Ion/Ioff ratio, device gain, and extremely low value of intrinsic delay and power dissipation, the proposed design is a suitable candidate for low-voltage low-power digital and analog applications.

Performance of 5-nm a-IGZO TFTs With Various Channel Lengths and an Etch Stopper Manufactured by Back UV Exposure

Abstract: Stable and fast-switching thin-film transistors and circuits incorporating 5-nm-thick amorphous-InGaZnO (a-IGZO) active layers are demonstrated, and their dependence on channel length is studied. Turn-on voltage shifts in the positive gate voltage direction as the channel length increases. A low area density of defects in the bulk a-IGZO, which is ultrathin, results in good stability under positive bias stress, whereas interdiffusion of electrons/electron donors from the highly doped source and drain regions to the channel edges results in the dependence of turn-on voltage on channel length. Stable operation of an 11-stage ring oscillator is achieved with a propagation delay time of ~97 μs/stage due to reduced gate-to-drain overlap capacitance and parasitic resistances.

Symmetrical unified compact model of short-channel double-gate MOSFETs

Abstract: An explicit charge-based unified compact drain current model for lightly doped or undoped DG MOSFETs is proposed. It takes into account the short-channel effects, the subthreshold slope degradation, the drain-induced barrier lowering and the channel length modulation effects. The model is valid and continuous in all regimes of operation and it has been validated by developing a Verilog-A code and comparing the model results of transfer and output characteristics with simulation results exhibiting an average error of about 3%. The efficient solution of the Lambert W function for the inversion charge and the symmetry of the model make it suitable for circuit simulation and allow fast and accurate simulations of the transistor characteristics.

Gradual channel approximation models for organic field-effect transistors: The space-charge field effect

Abstract: The gradual channel approximation is widely used for organic field-effect transistors with an assumption of linear potential profile across the channel. However, this is in contradiction with reported potential profiles. Here, we discuss linear and nonlinear potential profiles in the meaning of the space-charge field generated by injected carriers. The influence on current-voltage relation used for mobility evaluation in linear and saturated regions is proposed as well as transition between these states. In addition, the effect of the space-charge on the potential drop and field around the drain electrode in the saturation region is discussed.

A physics based compact model for drain current in AlGaN/GaN HEMT devices

Abstract: In this paper we present a physics based analytical model for the drain current I d in AlGaN/GaN high electron mobility transistors. The proposed model is developed based on the analytical 2-D electron gas density n s model developed previously by our group. The model includes important effects like velocity saturation, channel length modulation, short channel effect, pinch-off, mobility degradation, and self-heating. The model is in excellent agreement with the experimental data over a typical range of applied gate and drain voltages for various device geometries.

Modelling and simulation of saturation region in double gate graphene nanoribbon transistors

Abstract: Novel analytical models for surface field distribution and saturation region length for double gate graphene nanoribbon transistors are proposed. The solutions for surface potential and electric field are derived based on Poisson equation. Using the proposed models, the effects of several parameters such as drain-source voltage, oxide thickness and channel length on the length of saturation region and electric field near the drain are studied.

Channel-length-dependent transport and photovoltaic characteristics of carbon-nanotube-based, barrier-free bipolar diode.

Abstract: Carbon nanotube (CNT) diodes with different channel length between L = 0.6μm to 3.5 μm are fabricated on the same tube, and the electric and photovoltaic characteristics are investigated. It is found that although the open voltage of the diode increases rapidly for channel length L less than 1.0 μm, it saturates for longer channel devices. On the other hand, the short circuit current of the diode exhibites a clear peak at intermediate channel length of about 1.5 μm, a large leakage current via tunneling for short channel device and significantly decreased current for long channel device due to the increased recombination and channel resistance. The optimal channel length for a CNT diode in photovoltaic application is thus determined to be about 1.5 μm.

Nanowire Metal--Oxide--Semiconductor Field-Effect Transistors with Small Subthreshold Swing Driven by Body-Bias Effect

Abstract: We demonstrate metal–oxide–semiconductor field-effect transistors (MOSFETs) with small subthreshold swing (SS). The MOSFETs have a nanowire channel and three gates. A parasitic bipolar transistor formed in a fully depleted silicon-on-insulator MOSFET applies body bias to the MOSFET's channel and thus reduces the SS. Additionally, triple-gate operation makes the drain voltage smaller and provides current characteristics with a high on/off ratio and small hysteresis. As a result, SSs of the n- and p-type MOSFETs reach 6.6 and 5.2 mV/dec, respectively, in the range of current of six orders of magnitude. These features promise MOSFETs with low power consumption.

Benefits of cryo-implantation for 28 nm NMOS advanced junction formation

Abstract: In this paper, the integration benefits from cryogenic NMOS source drain extension implants on a state-of-the-art 28 nm logic flow are demonstrated and discussed. It is shown that device benefits, such as improved short channel effect, drain-induced barrier lowering and static random access memory yield improvement, can be achieved via damage engineering and enhanced dopant halo activation.

OFF-state induced threshold voltage relaxation after PBTI stress

Abstract: The influence of different relaxation biases on positive bias temperature instability (PBTI) recovery is investigated. The threshold voltage (V th ) relaxation after stress is found to be accelerated by OFF-state bias in comparison to zero volt recovery. 2D device simulations evidence an increase in the drain side channel potential as well as an increase in the minimum potential for short channel devices. The relaxation effect is attributed to an enhanced detrapping of charge carriers by the drain-gate electrical field and becomes significant for short channel device below 0.1 μm length.

The Analysis of Breakdown Voltage for the Double-gate MOSFET Using the Gaussian Doping Distribution

Abstract: This study has presented the analysis of breakdown voltage for a double-gate metal-oxide semiconductor field-effect transistor (MOSFET) based on the doping distribution of the Gaussian function. The double-gate MOSFET is a next generation transistor that shrinks the short channel effects of the nano-scaled CMOSFET. The degradation of breakdown voltage is a highly important short channel effect with threshold voltage roll-off and an increase in subthreshold swings. The analytical potential distribution derived from Poisson’s equation and the Fulop’s avalanche breakdown condition have been used to calculate the breakdown voltage of a double-gate MOSFET for the shape of the Gaussian doping distribution. This analytical potential model is in good agreement with the numerical model. Using this model, the breakdown voltage has been analyzed for channel length and doping concentration with parameters such as projected range and standard projected deviation of Gaussian function. As a result, since the breakdown voltage is greatly changed for the shape of the Gaussian function, the channel doping distribution of a double-gate MOSFET has to be carefully designed.

Oxide Thinning and Structure Scaling Down Effect of Low-Temperature Poly-Si Thin-Film Transistors

Abstract: In this paper, the gate oxide thickness, and the channel length and width of low-temperature poly-Si thin-film transistors (LTPS-TFTs) have been comprehensively studied. The scaling down of gate oxide thickness from 50 to 20 nm significantly improves the subthreshold swing (S.S.) of LTPS-TFTs from 1.797 V/decade to 0.780 V/decade and the threshold voltage VTH from 10.87 V to 5.00 V. Moreover, the threshold voltage VTH roll-off is also improved with the scaling down of gate oxide thickness due to gate capacitance density enhancement. The channel length scaling down also shows significant subthreshold swing S.S. improvement due to a decreasing of the channel grain boundary trap density Nt. However, the scaling down of channel length also increases the series resistance effect, resulting in the degradation of the field-effect mobility μFE. Therefore, the channel length dependence of field-effect mobility μFE is slightly different with different channel width due to the competition of channel grain boundary trap density effect and series resistance effect.

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

Abstract: We investigate the influence of voltage drop across the lightly doped drain (LDD) region and the built-in potential on MOSFETs, and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers. The model can predict the fringing-induced barrier lowering effect and the short channel effect. It is also valid for non-LDD MOSFETs. Based on this model, the relationship between threshold voltage roll-off and three parameters, channel length, drain voltage and gate dielectric permittivity, is investigated. Compared with the non-LDD MOSFET, the LDD MOSFET depends slightly on channel length, drain voltage, and gate dielectric permittivity. The model is verified at the end of the paper.

Impact of velocity saturation and hot carrier effects on channel thermal noise model of deep sub-micron MOSFETs

Abstract: This paper discusses the impact of the short channel effects, such as channel length modulation (CLM), velocity saturation effect (VSE) and hot carrier effect (HCE), on the channel thermal noise model of short channel MOSFETs. Based on the fundamental thermal noise theory, the channel thermal noise models are derived in four different cases considering the effect of CLM only, CLM and VSE, CLM and HCE, and the combine effect of CLM, VSE and HCE. The noise reduction due to the VSE is found to be completely cancelled out by the noise increment due to the HCE for all the operating conditions.

Low voltage current mirror

Abstract: The invention discloses a low voltage current mirror, and aims to solve the problem that output voltage swing is reduced because threshold voltage is wasted by the voltage redundancy of the conventional cascode current mirror. The low voltage current mirror comprises an input current source, a first P-channel metal oxide semiconductor (PMOS) tube, a second PMOS tube, a third PMOS tube, a first N-channel metal oxide semiconductor (NMOS) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube. The low voltage current mirror has a cascode output structure, output resistance is very high, and the influence of a load on output current is relatively small, so that the mirror image precision of the current mirror is very high; and a channel length modulation effect is rationally used by the structure, so that compared with the cascode current mirror, the current mirror has the advantages that the redundancy of the threshold voltage is reduced, and the output voltage swing is increased.

Controlling Characteristics of 4H-SiC(0001) p-Channel MOSFETs Fabricated on Ion-Implanted n-Well

Abstract: Fabricated were 4H-SiC p-channel MOSFETs in two types of ion-implanted n-well regions and in the n-type substrate as a control. Effects of the n-well structure on the electrical properties were investigated. P-channel MOSFETs fabricated in the uniform doped n-well by using multiple ion-implantations showed inferior on-state characteristics to that of the control MOSFET, while those fabricated in the retrograde n-wells by using single-shot ion-implantation without additional implantation to form the surface p-type region indicated improved channel properties. The Vth values were controlled by the impurity concentration and depth of the surface p-type region, and the values of channel mobility were nearly equal to that of the control MOSFET. Good sub-threshold characteristics for the type II devices were demonstrated.

Reduced Scale Resonant Tunneling Field Effect Transistor

Abstract: An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major axis, corresponding to channel length, and a minor axis that corresponds to channel width and is orthogonal to the major axis; (b) the channel length is less than 10 nm long; (c) the source is doped with a first polarity and has a first conduction band; (d) the drain is doped with a second polarity, which is opposite the first polarity, and the drain has a second conduction band with higher energy than the first conduction band Other embodiments are described herein

In-Plane Gate Transistors With a 40- $\mu\hbox{m}$ -Wide Channel Width

Abstract: An in-plane gate transistor with a GaAs/AlGaAs 2-D electron-gas channel about 40 μm in width is investigated. The saturation region and the drain current modulation at different gate bias voltages are observed despite the wide channel. The surface-induced channel depletion is suggested as the main mechanism for the turn-off of the drain current at - 10 V gate bias.