Showing papers on "Channel length modulation published in 2021"

High-Drain Field Impacting Channel-Length Modulation Effect for Nano-Node N-Channel FinFETs

Abstract: Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio have been developed after integrating a 14A nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. Under the lower gate voltage (VGS-VT) and the higher drain/source voltage VDS, the channel-length modulation (CLM) effect coming from the interaction impact of vertical gate field and horizontal drain field was increased and had to be revised well as the channel length L was decreased. Compared to the 28-nm MOSFETs, the interaction effect from the previous at the tested FinFETs on SOI substrate with the short-channel length L is lower than that at the 28-nm device, which means the interaction severity of both fields for nFinFETs is mitigated, but still necessary to be concerned.

Current-to-transconductance ratio technique for simultaneous extraction of threshold voltage and parasitic resistances in MOSFETs

Abstract: In this work, a current-to-transconductance ratio technique is proposed for simultaneous extraction of the threshold voltage (VT) and parasitic source (RS) and drain (RD) resistances in short channel metal–oxide–semiconductor field-effect transistors (MOSFETs). The proposed technique allows simultaneous extraction of RS, RD, and VT in any single MOSFET with the channel length modulation (CLM) and the structural asymmetry. The proposed method is experimentally verified through Si MOSFETs with intentional asymmetry by connecting an external resistor (Rext) to the source terminal. We experimentally confirmed that extracted RS, RD, and VT are independent of the drain bias (VDS) and intentional Rext employed for the asymmetry. We also compared the results with previously reported techniques.

Statistical and Electrical Modeling of FDSOI Four-Gate Qubit MOS Devices at Room Temperature

Abstract: This paper presents an electrical characterization and a compact modeling of FD-SOI four-gate qubit MOS devices, carried out at room temperature and in linear regime. The main figures of merit are extracted from average drain current curves using Y – function method. Poisson solver-based simulations are performed to interpret the experimental data, in particular the influence among gates and the effective channel length modulation. Furthermore, a drain current matching analysis between gates is conducted, and the main variability parameters are extracted. Our results, despite the unconventional device engineering, show a variability performance comparable to the state-of-the-art 28nm FD-SOI technology. Finally, a Lambert function based model is developed to validate both the electrical and statistical characterization. It is assumed, according to the experimental data, that the four gate device can be modeled as the series of four identical and independent transistors. Including the contribution of source and drain access resistance it has been possible to reproduce the device behavior at high external gates voltages.

CJFET Op-Amp without Current Mirrors for Low Temperature Applications

Abstract: This paper proposes operational amplifier’s (Op-Amps) architectures based on complementary field-effect transistors with p-n junction (CJFETs), in which the effect of channel length modulation on the systematic component of the Op-Amp’s zero offset voltage (V off ) is reduced. The peculiarity of the developed Op-Amp’s circuitry solutions is that due to the high self-adjusting symmetry of the static mode in terms of the gate-drain voltages of the dominant CJFETs, they provide a low V off level and increased values of the gain (GAIN). The computer simulation of Op-Amps in the LTSpice software (Analog Device, USA) showed that GAIN of the Op-Amps is more than 80 dB, and the systematic component of the zero offset voltage is within 30 μV in the temperature range up to -197°C. Op-Amp circuits of the proposed subclass can have low current consumption in static mode and can be performed not only on Si CJFETs, but also on the basis of wide-gap semiconductors (SiC CJFET, GaN CJFET or GaAs CJFET). Recommended applications of the developed architectures are analog interfaces of physical quantities of sensors for high-energy physics, medicine, and space instrumentation.

Analytical drain current and performance evaluation for inversion type InGaAs gate-all-around MOSFET

Abstract: This paper presents an analytical investigation of the drain current model for symmetric short channel InGaAs gate-all-around (GAA) MOSFETs valid from depletion to strong inversion using a continuous expression. The development of the core model is facilitated by the solution of the quasi-2D Poisson equation in the doped channel, accounting for interface trap defects and fixed oxide charges. Correction to short channel effects such as threshold voltage roll-off, drain induced barrier lowering, and subthreshold slope degradation is later introduced, complemented with channel length modulation, velocity saturation, and mobility degradation from surface roughness, leading to accurate mobile charge density for electrostatic capacitance–voltage and transport characterization. The effect of physical process parameters such as fin width, oxide thickness, and channel length scaling is thoroughly investigated in both on and off states of the transistor. The robustness of the model is reflected by the precise match with published experimental reports in the literature. An Ron of 1160 Ω μm is obtained from output characteristics and a switching efficiency improvement of 2.5 times is estimated by incorporating a high-κ dielectric into the GAA transistor. Numerical 3D simulations from TCAD corroborate the validity of the proposed model in all regions of operation.

A Surface Potential and Drain Current Model for Tri-Gate FinFET: Analysis of Below 10nm Channel Length

Abstract: A drain current model based on Lambert W function is analyzed for lightly doped (undoped) short channel tri gate FinFET (TG-FinFET). The channel length modulation (CLM), the effect of series resistance, mobility degradation and saturation velocity are included in the drain current model. Quantum mechanical effect (QME) is also included to achieve precise drain current for such a small channel device. The model is inspected mainly for two fin widths with two dielectric materials namely, silicon dioxide (SiO 2 ) and hafnium oxide (HfO 2 ). A complete study of electrical parameters including surface potential and the threshold voltage are addressed for both the dielectric materials. The threshold voltage is cross-examined by reported experimental results.

Reducing the Drain Leakage Current in a Double-Gate Junctionless MOSFET Using the Electron Screening Effect

Abstract: This study investigated the position of electrons and holes in the ON and OFF states of double-gate junctionless transistors, and then three structures were proposed to create an electron-filled region exposing the drain-side inside the channel to the electron screening effect. Formation of an electron cloud in the channel and on the drain-side damps the electric field resulting from the drain voltage as the electric field passes through the electron cloud before reaching the main channel. Accordingly, in the structure with a drain-side gate, with the electric field decay introduced by the drain to the main channel, the carrier density increased compared to other structures, eventually reducing drain leakage current and improving the channel length modulation (CLM), threshold voltage, drain induced barrier lowering effect, and subthreshold slope in this structure. In the N+ pocket structure, despite the decrease in the electric field resulting from the drain voltage, the drain leakage current and the CLM were increased. In the N+ SiGe pocket structure, although the electric field resulting from the drain voltage along the channel length was reduced compared to the main structure, the drain leakage current and CLM experienced an increase. Moreover, the results showed that at low drain voltages, the drain leakage current in the N+ pocket structure was higher than that of the N+ SiGe pocket, but at high drain voltages, the order was reversed.

Enhanced Performance of Strained Graphene Wrapped Channel Cylindrical FET

Abstract: In order to perform logic and memory operation with high speed and accuracy, transistors should have high ON/OFF current ratio and high charge carrier mobility. But it is difficult to achieve both of these criteria in a single transistor. Graphene is considered as one of the most promising candidates due to its high mobility. But graphene field effect transistor (GFET) gives very low ON/OFF current ratio as graphene is a semi-metallic material. In this work, we have modeled strained graphene on silicon FET with high k dielectric material like HfO 2 , TiO 2 and obtained notable improvement in the ON/OFF current ratio along with the drain current. But the structure suffers from significant channel length modulation effect. Finally, we have proposed a cylindrical FET structure with strained graphene layer to minimize the channel length modulation effect while maintaining the high ON/OFF current ratio and high charge carrier mobility.

Strategy for Simulation of Analog Circuits with GCSOI MOSFET using BSIM SOI model

Abstract: This work presents a simulation strategy to simulate Graded-Channel SOI MOSFET electrical characteristics using BSIM SOI SPICE model. The use of uniformly doped transistor model is possible by adjusting low field mobility, degradation mobility factors and parameters related to channel length modulation and DIBL effects. A good agreement with experimental data was achieved at device level. The simulation strategy is validated through the simulation of common-source current mirrors using adjusted SPICE model parameters, presenting the same trends of experimental results available in the literature.

Current mismatch reduction in charge pumps using regulated current stealing-injecting transistors for PLLs

Abstract: A charge pump for phase locked loops (PLL) with a novel current mismatch compensation technique is proposed. The proposed circuit uses a simple yet effective current stealing-injecting (CSI) technique and feedback to reduce mismatch between the negative-channel-metal-oxide (NMOS) and positive-channel-metal-oxide (PMOS) transistors. The current stealing transistor steals the current from a replica branch and mirrors it to the output where it is added to the output branch by the injecting transistor. A feedback mechanism is used to set the drain voltages of both branches to be equal and mitigate channel length modulation and ensure high accuracy. The proposed circuit was designed on Silterra 130nm technology and simulated using Cadence Spectre. The simulation results show that the proposed circuit yields a maximum of 0.107% and minimum of 0.00465% current mismatch while operating at a low supply voltage of 800mV for a range of 100mV to 700mV. The proposed design uses only one rail-to-rail op amp for compensating the mismatch and an addition of 4 transistors and utilizing 75% of the supply voltage for high voltage controlled oscillator (VCO) tuning range.

Protruding gate transistor and method of producing same

Abstract: A structure of a protruding gate transistor is disclosed. The protruding gate transistor comprising a substrate, a source region, a drain region, a channel extension anchor, a channel layer, and gate structure. The gate structure comprising a gate insulator layer, and a gate conductor layer. The channel layer is formed to be protruding from the substrate to extend the length of the channel of the protruding gate transistor and alleviate from channel length modulation.