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Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.


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Patent
07 Nov 2006
TL;DR: In this article, the authors proposed to suppress short channel effects by incorporating buried isolation regions into a transistor below source/drain extension regions and between deep source/drains regions and the channel region and particularly between the halo regions.
Abstract: Disclosed are embodiments of improved MOSFET and CMOS structures that provides for increased control over short channel effects. Also disclosed are embodiments of associated methods of forming these structures. The embodiments suppress short channel effects by incorporating buried isolation regions into a transistor below source/drain extension regions and between deep source/drain regions and the channel region and, particularly, between deep source/drain regions and the halo regions. Buried isolation regions between the deep source/drain regions and the channel region minimize drain induced barrier lowering (DIBL) as well as punch through. Additionally, because the deep source/drain regions and halo regions are separated by the buried isolation regions, side-wall junction capacitance and junction leakage are also minimized.

15 citations

Proceedings ArticleDOI
B. Lemaitre1
08 Dec 1991
TL;DR: In this article, an improved analytical LDD (lightly doped drain)-MOSFET model for digital and analog circuit simulation in the deep submicron region is described, which includes all short and narrow channel effects and a substrate current model.
Abstract: An improved analytical LDD (lightly doped drain)-MOSFET model for digital and analog circuit simulation in the deep-submicron region is described This model includes all short and narrow channel effects and a substrate current model Special emphasis was placed on the voltage-dependent effective channel length and series resistance of LDD devices The voltage-dependent channel length and series resistance of LDD devices are measured electrically, verified with capacitance measurements, and introduced into the model >

15 citations

Journal ArticleDOI
TL;DR: In this paper, a new analytical, physics-based I-V model for hot-electron damaged submicrometer p-type MOSFETs was developed based on a pseudo-two-dimensional approach, incorporating the effect of the spatial distribution of trapped electrons and can be used to calculate the degraded channel electric field and potential distribution.
Abstract: In a p MOSFET, trapped electrons in the gate oxide due to hot-carrier stress reduce the effective channel length by inverting the surface from an n -type surface to a p -type surface and extend the p drain region. To describe the channel shortening, this paper presents a new analytical, physics-based I - V model for hot-electron damaged submicrometer p -type MOSFETs. The model was developed based on a pseudo-two-dimensional approach, it incorporates the effect of the spatial distribution of trapped electrons and can be used to calculate the degraded channel electric field and potential distribution. The model can also describe the time-dependence of degraded drain current with stress time.

15 citations

Journal ArticleDOI
TL;DR: The noise in MOSFETs at zero drain bias was found to be somewhat larger than the thermal noise of the output conductance gdo at that bias as discussed by the authors, and the effect was most pronounced at 300°K and has practically disappeared at 77°K.
Abstract: The noise in MOSFETs at zero drain bias is found to be somewhat larger than the thermal noise of the output conductance gdo at that bias The effect is most pronounced at 300°K and has practically disappeared at 77°K The effect is attributed to the large transverse field at the surface of the channel; the temperature dependence of the effect is as yet unexplained

15 citations

Journal ArticleDOI
TL;DR: In this article, a simple solution of the two dimensional Poisson equation is derived at the SiSiO 2 interface for the region bounded by the source and the drain.
Abstract: Using the well known El-Mansy-Ko method, a simple solution of the two dimensional Poisson equation is derived at the SiSiO 2 interface for the region bounded by the source and the drain. The solution is valid for long channel as well as short channel MOSFETs. The effect of variable values of the depletion depth is incorporated using the WKB approximation. The solution yields a new model of the subthreshold voltage of a short channel MOSFET. The solution also provides mathematical justification of the intuitive assumptions made by Hsu, Muller and Hu in their paper on punch through currents in short channel MOSFETs. Since the single solution gives both the drain induced high field, DIHF, and the drain induced barrier lowering, DIBL, it also yields an analytical relation between them. The DIBL increases approximately expnentially as E max decreases. The results obtained from this model are in agreement with the numerical simulations and are consistent with the known experimental results.

14 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202230
202111
202016
201915
20189