Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

Compact model of short-channel MOSFETs considering quantum mechanical effects

Abstract: A unified analytical model for the I – V characteristics of short channel bulk nMOSFETs with 〈1 0 0〉 Si surface orientation valid for the subthreshold, linear and saturation regions is presented In this model, the inversion layer charge is obtained considering quantum mechanical (QM) effects The field dependent mobility variations, velocity saturation of carriers and secondary effects such as DIBL and channel length modulation have been incorporated in this model There is a smooth transition in the current from subthreshold to above threshold and also from linear to saturation regions of operation This results in highly continuous channel conductance ( g ds ) and transconductance ( g m ), which are important circuit parameters in small signal analysis In addition, the result of a few benchmark tests shows that the model holds good promise for analog circuit design The model has been implemented in SABER, a circuit simulator The result from the model shows an excellent agreement with two-dimensional device simulator and experimental data

Submicron Channel MOSFET Using Focused Boron Ion Beam Implantation into Silicon

Abstract: A new submicron channel length device, ion beam MOSFET (IB-MOS), is proposed as an effective application of focused-ion-beam implantation into silicon. The effective channel region of this device is formed by the one line scan of a 16 keV, focused B+ ion beam (diameter: 0.2 µm, current density: 50 mA/cm2) in an As+ implanted n- gate region between the source and drain. It is demonstrated by two dimensional device simulation that significant improvements in current gain, drain breakdown voltage and short-channel threshold effect are achieved for IB-MOS devices with 0.8 µm source-drain spacing. A fabricated IB-MOS device verifies the results of the simulation, except for the current gain, because of the high impurity effect in the channel region, which could be improved by choosing appropriate channel implantation conditions.

Junctionless Poly-Si Nanowire FET With Gated Raised S/D

Abstract: The short-channel effect (SCE) is an important issue in CMOS technology. In this paper, a junctionless (JL) poly-Si nanowire FET (NW-FET) with gated raised source/drain (S/D) was demonstrated to suppress the SCE. The gated raised S/D structure enhances the control of the channel by the gate. Therefore, a JL poly-Si NW-FET with the gated raised S/D exhibits reduced drain-induced barrier lowering and less channel length modulation effect. Additionally, when the gate bias exceeds the flat-band voltage, a JL poly-Si NW-FET with gated raised S/D exhibits a low parasitic S/D resistance owing to the formation of an accumulation layer in its S/D, which is useful for multi-gate-oxide applications. However, the gated raised S/D shows a high gate-induced drain leakage current in the off state. Therefore, the gate electrode of the gated raised S/D must be designed carefully to prevent high off current.

Potential, field and carrier distribution in the channel of junction field-effect transistors

Abstract: The operation mechanism of field-effect transistors (FET) was investigated by the measurements of the potential distribution in the channel using a tungsten needle as a probe in alloyed junction type FET in operation. The field distribution and the free carrier distribution were obtained as the first and the second derivative of the measured potential distribution. It is clear that, before the current saturation, from the source to the drain the electrically neutral channel exists. In this region the ionized impurity density and the carrier density are equal and the field toward the gate can be neglected. Contrary to this, in the channel at the drain side after the current saturation, the space charge layer extending from the gates reaches near the channel centre and the field to the gate direction becomes extremely high. In this region, an effective channel is formed in which the free carriers decrease toward the gate. At the centre of the effective channel, the electrical neutrality almost holds. Almost all of the voltage after the current saturation are spent in this region which is independent of the source side. In this short high field region, the field seems to be even in the velocity saturation region ( E >1·5×10 4 V/cm) of the carriers. The highest field region is rather outside of the gates. The potential and the carrier distribution in the channel at the drain side show a fairly good agreement with the theoretical calculation analysed in this paper.

Impact of Substrate Resistance on Drain Current Noise in MOSFETs

Abstract: This paper identifies the physical origin and contribution mechanism of substrate induced channel thermal noise in MOSFETs. Resistance of the substrate generates potential fluctuations that in turn produce additive channel noise via the channel depletion capacitor. The additive noise may result in a frequency dependence of the drain current noise due to a pole associated with the Rsub-Cdepi network. Its bias and length dependencies conforms to those of reported excess noise, it thus may exaggerate the amount of the channel thermal noise factor.