Topic
Channel length modulation
About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.
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TL;DR: In this article, a physics-based compact model for drain current I d and intrinsic gate-drain and gate-source capacitances C GS and C GD in AlGaN/GaN high electron mobility transistors is presented.
Abstract: In this paper we present a physics-based compact model for drain current I d and intrinsic gate–drain and gate–source capacitances C GS and C GD in AlGaN/GaN high electron mobility transistors. An analytical expression for the 2-DEG charge density n s , valid in all the regions of device operation is developed and applied to derive current and capacitances. The drain current model includes important physical effects like velocity saturation, channel length modulation, short channel effect, mobility degradation effect, and self-heating. The expression for n s is used to derive a model for C GS and C GD applicable in all the regions of device operation. The parameters introduced in the model have a clear link to the physical effects facilitating easy extraction of parameter values. The model is in excellent agreement with experimental data for both drain current and capacitances over a typical range of applied voltages and device geometries.
100 citations
TL;DR: In this article, bias stress instability in top-contact pentacene thin film transistors was observed to be correlated not only to the channel but also to the metal/organic contact, and the drain current decay under bias stress results from the combination of the contact resistance change and the threshold voltage shift in the channel.
Abstract: Bias stress instability in top-contact pentacene thin film transistors was observed to be correlated not only to the channel but also to the metal/organic contact. The drain current decay under bias stress results from the combination of the contact resistance change and the threshold voltage shift in the channel. The contact resistance change is contact-metal dependent, though the corresponding channel threshold voltage shifts are similar. The results suggest that the time-dependent charge trapping into the deep trap states in both the contact and channel regions is responsible for the bias stress effect in organic thin film transistors.
95 citations
Patent•
10 Apr 1995TL;DR: In this article, a high voltage PMOS or NMOS transistor was truncated by truncating gate field oxide 43 so that drain region 42 may be implanted closer to channel region 49 than possible otherwise.
Abstract: A high voltage PMOS or NMOS transistor 7 has improved on-resistance by truncating gate field oxide 43 so that drain region 42 may be implanted closer to channel region 49 than possible otherwise. By shortening the physical distance d2 between drain 42 and channel region 49, the drain to source on-resistance of the high voltage device is reduced and the performance of high voltage device 7 is thereby improved.
95 citations
TL;DR: In this article, the authors present an accurate analytical IGFET model for short-channel devices down to sub-half micron channel lengths, which is described by a single drain current equation, valid for both weak and strong inversion regions of device operation.
Abstract: We present an accurate analytical IGFET model (PCIM), for short-channel devices down to sub-half micron channel lengths. The model is described by a single drain current equation, valid for both weak and strong inversion regions of device operation. The model contains a new velocity-field (/spl upsi/-/spl epsi/) relation for carriers in the channel region. Combining this relation with the channel length modulation expression, obtained using engineering approximations to the two-dimensional fields near the drain end in saturation, results in an accurate drain conductance equation. The value for the carrier saturated velocity extracted from the I-V data for different CMOS technologies is 7-8/spl times/10/sup 6/ cm/s for electrons and 5-6/spl times/10/sup 6/ cm/s for holes, consistent with the reported values. The model not only predicts accurate output conductance, which is important for analog design, but also accurately simulates intrinsic gate capacitances for short channel devices. Since the model is inherently continuous, device conductances and capacitances are smooth and continuous at the transition points. This continuity results in enhanced convergence properties of the circuit simulator SPICE. Because the model is physically based, the temperature dependence of device characteristics in the temperature range 0-120/spl deg/C can easily be predicted simply by taking the temperature dependence of the threshold voltage, carrier mobility and velocity saturation parameters. >
95 citations
TL;DR: In this article, the authors proposed a method to determine the channel length and gate voltage-dependent source-and-drain series resistance of an LDD MOSFET and a modal for the LDD device current at small drain-source voltage.
Abstract: The introduction of n- regions makes an LDD MOSFET behave differently from a conventional MOSFET. The source-and-drain series resistance, which consists of the n+-and-n-regions, shows a strong dependence on the gate bias. Also, the apparent effective length can vary with gate bias. These special features cause the traditional method to determine effective channel length and series resistance inapplicable. In this letter, we propose a method to determine the "intrinsic" channel length and gate-voltage-dependent source-and-drain series resistance of an LDD MOSFET and a modal for the LDD device current at small drain-source voltage.
95 citations