Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

Twin channel Lorentz coupled depletion width modulation effect magnetic field sensor

Abstract: A high sensitivity, low noise, broad bandwidth, twin channel conduction Lorentz channel coupled semiconductive field sensor device is described. The conductive channels are configured to create exceptionally narrow, undepleted conduction zones of approximately filamentary form. The filamentary conductive channels so formed are provided with a common source at one end of each channel and a separate drain at the other end thereof. The independent drains are spaced apart by a narrow area of semiconductive material. Magnetic fields may be utilized to create a Lorentz voltage in a region between the two conductive channels to vary the amount of current received at the two drains by utilizing the depletion width modulation effects of the Lorentz voltage upon the boundaries defining the conductive channel portions. Modulation of the depletion zone widths and depths along the channel sides effectively move the streams of carriers and the conductive channel areas to conduct more current to one drain more than another. This develops a differential drain current balance which can be utilized to provide an output signal. Width and length criteria for defining the filamentary channel structures are described for the ultimate desired configuration and size which are to be obtained. As noted, operation of the device is based upon Lorentz voltage modulation of the width and depth of the depletion zone boundaries defining the conductive channel. The Lorentz voltage is created in an area of semiconductive material coupling the two filamentary channels. An increased signal output is obtained by reducing the width of the filamentary channels to eliminate excess carriers normally found in wide channel devices and, further, by making the depletion zones as large a portion of the total channel widths as can be obtained.

New experimental findings on hot carrier effects in sub-0.1 μm MOSFET's

Abstract: The behaviors of the substrate current and the impact ionization rate are investigated for deep submicron devices in a wide temperature range. New important features are shown for the variations of the maximum substrate current as a function of applied biases and temperature. It is found that the gate voltage V/sub gmax/, corresponding to the maximum impact ionization current conditions, is quasi-constant as a Function of the drain bias for sub-0.1 /spl mu/m MOSFET's in the room temperature range. At low temperature, a substantial increase of V/sub gmax/ is observed when the drain voltage is reduced. It is also shown that, although a significant enhancement of hot carrier effects is observed by scaling down the devices, a strong reduction of the impact ionization rate is obtained for sub-0.1 /spl mu/m MOSFET's operated at liquid nitrogen temperature in the low drain voltage range. >

Analytical current equation for short channel SOI multigate FETs including 3D effects

Abstract: Current flow in short-channel multigate FETs is strongly influenced by 2D or even 3D effects. In subthreshold operation the channel current is located in the device center, whereas above threshold the channel moves to the silicon-to-oxide interface. This movement of the most leaky path can result in an abnormal behavior in the transconductance. In this paper an analytical current equation for lightly doped devices is proposed which takes into account these effects. The leakage current is calculated from a three-dimensional solution of the electrostatic potential at the barrier within the channel. For the current above threshold, which is located at the channel surface, a bulk MOS model is superposed. The final current equation takes into account short-channel effects as threshold voltage shift, drain-induced barrier lowering, subthreshold slope degradation and the movement of the most leaky path within the channel cross section. The model has been benchmarked by numerical results and is in good agreement down to a channel length of 30 nm.

Channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors

Abstract: This paper presents an experimental analysis of channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors. It is shown that the increase of the drain current and transconductance is more pronounced with the reduction of the length of the transistor close to the source (L1), and, differently from the symmetric self-cascode, suffers little influence of the length close to the drain (L2). On the contrary, the output conductance of symmetric and asymmetric threshold voltage structures is benefited by the increase of L2 and L1, although the asymmetric structure may offer a reduction of up to one order of magnitude in comparison to the symmetric one. It results in larger intrinsic voltage drain for asymmetric devices. This increase has shown to reach more than 20 dB for similar dimensions, or allow for dimension reduction without intrinsic gain degradation.

A discrepancy in the elementary theory of MOSFET modeling

Abstract: The elementary theories of flicker noise in MOSFET’s operating at low drain bias evaluate the spectrum SVeq8f) of the equivalent gate noise emf δVeq under the assumptions of an effective mobility μeff that is independent of the gate voltage Vg and of a carrier number in the channel that varies linearly with the gate voltage We show here that this introduces an error I2d/[g2m(Vg—VT)2] in the calculated results Experiments show that this error can be significant, so that it makes some existing interpretations of SVeq(f) doubtful The error comes about because at a given drain current Id the transconductance gm for large Vg−VT is smaller than the elementary theory predicts This affects most MOSFET modeling at low drain bias