Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

A simple and continuous MOSFET model

Abstract: A simple CAD model is proposed for the short-channel enhancement-mode MOSFET. The conventional use of drain bias modulation of channel length to describe saturation characteristics has been discarded and replaced by drain bias enhancement of channel velocity. The model possesses continuity of current, transconductance and output conductance throughout the triode, and saturation ranges of operation. It has been tested against experimental transistors and against two-dimensional numerically simulated transistors, and has given satisfactory results in all cases. The model is based on good physics, is easy to understand, is straightforward to use, and is computationally efficient.

An analytical drain current model for submicrometer and deep submicrometer MOSFET's

Abstract: In this paper, we present a new, analytical, and physics-based drain current model for both submicrometer and deep submicrometer MOSFET's. The model was developed by starting from a two-dimensional (2D) Poisson equation and using the energy balance equation. Using the present model, we can clearly see that the drain current increases with decreasing channel length due to a larger average channel mobility at shorter channel length. The formulas for the saturation drain voltage and the drain current can be reduced to their corresponding well-known formulas in the submicrometer range. The accuracy of the presented model has been verified with the experimental data of metal-oxide-semiconductor (MOS) devices with various geometries.

Planar junction-gate field-effect transistors

Abstract: A junction-gate field-effect transistor is provided with its channel extending from the source to the drain in a direction normal to the plane of the substrate. The length of the channel is thereby substantially shorter than where the channel extends parallel to the plane of the substrate. The shorter channel provides faster switching speed and increased transconductance of the transistor.

MOS field effect transistor having source/drain regions surrounded by impurity wells

Abstract: Disclosed is a MOSFET for controlling the flow of a large number of carriers from one source/drain region to the other source/drain region by applying a voltage to a gate. This MOSFET includes a semiconductor substrate and a transistor. The transistor includes a gate provided on the semiconductor substrate, one source/drain region and the other source/drain region both having a first conductivity type. The MOSFET includes first and second wells of a second conductivity type formed apart from each other on opposite sides of the gate in the main surface of the semiconductor substrate. The first well is such a small well as to accommodate only one source/drain region, while the second well is such a small well as to accommodate only the other source/drain region. The one source/drain region and the other source region are formed in the first and second wells, respectively. No distortion due to thermal stresses remains in the resultant MOSFET, and consequently a highly reliable MOSFET is obtained.