Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

A 65nm CMOS low-power, low-voltage bandgap reference with using self-biased composite cascode opamp

Abstract: In this paper, we present a low-voltage low-power CMOS bandgap voltage reference (BVR) based on the self-cascode self-biased op-amp. The current mirror mismatch error resulting from the channel length modulation (CLM) effect has also been compensated by using composite transistors. This proposed circuit, implemented in 65nm IBM CMOS process, which generates a reference of 364mV from a power supply of the 1.2V and consumed the 28 μW at room temperature. The power supply rejection ratio is greater than 60 dB for frequency below 10 kHz. The proposed bandgap achieves a temperature coefficient(TC) of 4.7ppm/°C without trimming for the temperature range(TR) from 0°C to 100°C and the 0.75mV/V of ±10% supply voltage variations.

Channel-length-independent hot-carrier degradation in analog p-MOS operation

Abstract: The hot-carrier degradation of p-MOSFETs in analog operation is investigated. In accordance with analog operation requirements, the damage is characterized by the drain conductance and the data are taken from devices with channel lengths between 1 and 10 mu m. In the important saturation range, a strong channel-length-independent degradation of the drain conductance is found. This result is explained by a simple analytic model. Other parameters such as the drain current or the transconductance show the usual channel length dependence. These results show that an increase in channel length does not generally solve problems related with hot-carrier degradation. Furthermore, the common digital hot-carrier constraints are shown to be insufficient to cover analog applications. >

Semiconductor integrated circuit device and fabrication method

Abstract: The threshold voltages of transistors are set by controlling the amount of overlap in the direction of channel length between a channel region and a source region and the amount of overlap in the direction of channel length between the channel region and a drain region, whereby, in a semiconductor integrated circuit device in which transistors having different threshold voltages or different channel widths are mounted together, the ion injection conditions for the channel regions can be shared, thereby reducing the number of masks and the number of processing steps.

Effect of channel length on the threshold voltage degradation of hydrogenated amorphous silicon TFTs due to the drain bias stress

Abstract: The threshold voltage (VT) degradation of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) with various channel lengths of 2–100 μm has been investigated. In the presence of a drain bias, the VT degradation of a short channel a-Si:H TFT was less than that of a long channel TFT. After 30 000 s DC bias stressing, the VT shift of a short channel TFT (2 μm) was 0.35 V, while that of a long channel TFT (10 μm) was 0.6 V. The short channel effect on the VT degradation under the drain bias was negligible when the channel length exceeded 10 μm. The less VT degradation in a short channel a-Si:H TFT can be explained by the defect creation model that the VT shift is proportional to the number of carriers induced in the channel. In the presence of a drain bias, a short channel a-Si:H TFT has the smaller carrier concentration than a long channel TFT, so that a short channel a-Si:H TFT creates less defect states than a long channel TFT. The experiment with different channel widths of 100–500 μm showed no remarkable difference as observed in the case of channel length variation.

One-pin automatic tuning of MOSFET resistors

Abstract: Methods and apparatus for automatic tuning of MOSFET resistors providing accuracy and linearity throughout process and temperature variations. In accordance with the methods, the source and drain of a MOSFET device are biased in a balanced manner around a common mode voltage using a circuit controlling the gate voltage of the MOSFET to set the current through the MOSFET responsive to the value of a resistor. Operating MOSFETs, such as in MOSFET-C filters, with the same device conductivity type, gate bias, substrate voltage and signal common mode voltage provides linear MOSFET resistors, accurately set by a single resistance value. Use of an external resistor provides a single pin setting of MOSFET resistances, that may be independent of temperature and process variations. Various embodiments are disclosed.