Topic
Channel length modulation
About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.
Papers published on a yearly basis
Papers
More filters
04 Jun 2013
TL;DR: In this article, the authors elucidate the development of SOI-MOSFET using different gates like single, double, triple and gate all around structures, which is used for reducing the Parasitic Capacitances.
Abstract: This Paper elucidate the development of SOI-MOSFET using different gates like single, double, triple and gate all around structures. It is the Si MOSFET that is a fundamental device in the development of very high density Integrated Circuits. Thus SOI Technology is used for reducing the Parasitic Capacitances. Improvement in the electrostatic control by gate of the channel is done with the increase in effective number of gates. It minimizes short-channel effect which arises due to the lines of electric field from source and drain affecting control of the channel region. The technologies like Double-gate (top and bottom gate) SOI MOSFET and the Gate-all-Around (GAA) helps to suppress various short channel effects like Drain-Induced Barrier Lowering (DIBL) and degradation in Subthreshold slope. Nano MOSFETs are now the requirements of nano electronics and it is the Gate-all-Around MOSFET which is employed in silicon Nano wires.
9 citations
Patent•
27 Nov 2013
TL;DR: In this paper, a low-power-source-dependency band-gap reference voltage circuit design based on the PTAT current was proposed, in which a starting circuit, a reference voltage generating circuit and a reference buffering output circuit are used to drive a lowresistance load and meanwhile providing various voltage references.
Abstract: The invention discloses the low-power-source-dependency band-gap reference voltage circuit design based on the PTAT current. The low-power-source-dependency band-gap reference voltage circuit design comprises a starting circuit, a reference voltage generating circuit and a reference buffering output circuit, wherein the reference voltage generating circuit is composed of three parts including a cascode current mirror circuit, a positive temperature coefficient PTAT current generating circuit and a negative temperature coefficient current generating circuit. The starting circuit is used for starting the reference voltage generating circuit after being powered on. The reference buffering circuit is used for reducing the output resistance to drive a low-resistance load and meanwhile providing various voltage references. According to the low-power-source-dependency band-gap reference voltage circuit design based on the PTAT current, the cascode PTAT current generating circuit is used for being coordinated with an external circuit to generate the reference voltage with the stable performance and the zero temperature coefficient, and meanwhile the method of separating an external power source from the bias voltage required by the circuit is used for greatly reducing the power source dependency caused by the channel length modulation effect of an MOS device.
9 citations
TL;DR: An engineering model of the short-channel NMOS transistor which is applicable to both room-temperature and cryogenic device operation is presented and is a novel method to account for the bulk charge effect in the presence of drift velocity saturation, channel length modulation, charge sharing by the drain and source, and temperature dependence of the critical field.
Abstract: An engineering model of the short-channel NMOS transistor which is applicable to both room-temperature and cryogenic device operation is presented. The model incorporates the nonuniversal dependence of the effective channel mobility on the effective vertical field, which is ignored in room-temperature device models. Described also is a novel method to account for the bulk charge effect in the presence of drift velocity saturation, channel length modulation, charge sharing by the drain and source, and temperature dependence of the critical field. The proposed model is verified by comparison with experimental device characteristics obtained over a wide range of terminal voltages, temperatures, and channel lengths. >
9 citations
Patent•
09 Sep 1992TL;DR: In this paper, a thin film transistor (TFT) capable of reducing leakage current on the occasion when the transistor is OFF and lowering the resistance of an interconnection layer connected to source/drain regions and a method of manufacturing the same are disclosed.
Abstract: A thin film transistor (TFT) capable of reducing the leakage current on the occasion when the transistor is OFF and lowering the resistance of an interconnection layer connected to source/drain regions and a method of manufacturing the same are disclosed. In the thin film transistor, the length in the channel width direction of a polycrystalline silicon film 15 in junction parts 15c of a pair of source/drain regions 15b and a channel region 15a is smaller than the length in the channel width direction of polycrystalline silicon film 15 in source/drain regions 15b. Accordingly, the leakage current generated in junction parts 15c on the occasion when the TFT is OFF is reduced. In addition, it is unnecessary to reduce the length in the channel width direction of source/drain regions 15b, so that the resistance of an interconnection layer connected to source/drain regions 15b is lowered as compared to the conventional one.
9 citations
Patent•
31 Mar 1975
TL;DR: In this paper, the use of MOSFET to avoid punch-throughs while, at the same time shortening channel length to improve high frequency characteristics was discussed, and the channel length was reduced.
Abstract: PURPOSE:Use of MOSFET to avoid punch-throughs while, at the same time shortening channel length to improve high frequency characteristics.
9 citations