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Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.


Papers
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Journal ArticleDOI
TL;DR: In this article, a simple threshold voltage expression based on an approximate three-dimensional analysis has been obtained for MOSFET's with the LOCOS isolation structure, and the results match the experimental data.
Abstract: A simple threshold voltage expression based on an approximate three-dimensional analysis has been obtained for MOSFET's with the LOCOS isolation structure. It predicts both the short-channel and the narrow-width effects on the threshold voltage of MOSFET's, and the results match the experimental data. In addition, the threshold expression is more general than any other existing models. It includes all the relevant device parameters, such as the drain voltage, the oxide and surface charges, and the fringe field through the oxide sidewalls.

9 citations

Patent
01 Jul 2003
TL;DR: In this paper, a digital-analog converter (DAC) cell circuit includes a current source, a first resistor, a second resistor and a gate receiving a first control signal.
Abstract: A digital-analog converter (DAC) cell circuit. The circuit includes a current source, a first resistor, a second resistor, a first MOSFET, a second MOSFET, a third MOSFET and a forth MOSFET. The first MOSFET has a source and a drain connected to the current source and the first resistor, respectively, and a gate receiving a first control signal. The second MOSFET has a source and a drain connected to the current source and the second resistor, respectively, and a gate receiving a second control signal. The third MOSFET has a source and a drain connected to the source and drain of the first MOSFET, respectively, and a gate receiving a third control signal. The fourth MOSFET has a source and a drain connected to the source and drain of the second MOSFET, respectively, and a gate receiving a fourth control signal. The third control signal is a signal delayed of the first signal and the forth control signal is a signal delayed of the second signal. The delayed control signal can be used to control the slew rate of current DAC cell, thus reduce the package inductance induced L di/dt noise. Also it can be used to reduce the voltage fluctuations during current switching so as to get fast settling current.

9 citations

Journal ArticleDOI
TL;DR: In this paper, two novel structures for silicon on insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) with nanoscale dimension and superior electrical performance were introduced.

9 citations

Proceedings ArticleDOI
01 Dec 2008
TL;DR: In this paper, an analytical MOSFET model for 20 nm CMOS was proposed, which includes the gate voltage dependence of the channel length modulation parameter and demonstrated that the model can predict the current voltage characteristics with in good accuracy for n-channel and p-channel MOS-FETs down to 20 nm.
Abstract: This paper describes an analytical MOSFET model for 20 nm CMOS The model includes the gate voltage dependence of the channel length modulation parameter It is found that the channel length modulation parameter extracted from experimental data has remarkable gate voltage dependence in sub 65 nm region The dependence has been successfully modeled and included in an analytical MOSFET model This model can predict the current - voltage characteristics with in good accuracy for n-channel and p-channel MOSFETs down to 20 nm

9 citations

Patent
28 Jan 1999
TL;DR: In this article, a transistor having a longer channel length and serving as a reference, and a transistor with a shorter channel length are prepared to be subjected to effective channel length extraction, and the values of a function (F) are calculated which are defined by the difference between the rate of change in the total drain-to-source resistance and the product of a channel resistance per unit length.
Abstract: A transistor having a longer channel length and serving as a reference, and a transistor having a shorter channel length and to be subjected to effective channel length extraction are prepared (step ST1.1). A hypothetical point at which a change in a total drain-to-source resistance is estimated to be approximately zero when a gate overdrive is slightly changed is extracted in a mask channel length versus total drain-to-source resistance plane. The values of a function (F) are calculated which are defined by the difference between the rate of change in the total drain-to-source resistance and the product of a channel resistance per unit length and the rate of change in a mask channel length at the hypothetical points (step ST1.6). A true threshold voltage of the transistor having the shorter channel length is determined by a shift amount (δ) which minimizes the standard deviation of the function (F) determined in the step ST1.7 (step ST1.10). A resistance-based method thus extracts an effective channel length and a series resistance with increased accuracy.

9 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202230
202111
202016
201915
20189