Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

Low On-Resistance in Normally-Off 4H-SiC Accumulation MOSFET

Abstract: In our previous paper [1], we simulated an accumulation-mode MOSFET with an epitaxial layer channel (epi-channel) that had a high channel mobility. In this paper, we experimentally show that channel mobility is enhanced by the epi-channel. On varying the thickness of the epi-channel, the channel mobility improved from a few cm2/Vs to 100 cm2/Vs. Finally, we show that the “Normally-off” accumulation MOSFET with a 720 V breakdown voltage has a low on-resistance (10.4 m1cm2) and that the 3 × 3 mm2 accumulation MOSFET operates over 10 A and its on-resistance is 19 m1cm2.

Analysis of Short Channel Effects Using Analytical Transport Model For Double Gate MOSFET

Abstract: The analytical transport model in subthreshold regime for double gate MOSFET has been presented to analyze the short channel effects such as subthreshold swing, threshold voltage roll-off and drain induced barrier lowering. The present approach includes the quantum tunneling of carriers through the source-drain barrier. Poisson equation is used for modeling thermionic emission current, and Wentzel-Kramers-Brillouin approximations are applied for modeling quantum tunneling current. This model has been used to investigate the subthreshold operations of double gate MOSFET having the gate length of the nanometer range with ultra thin gate oxide and channel thickness under sub-20nm. Compared with results of two dimensional numerical simulations, the results in this study show good agreements with those for subthreshold swing and threshold voltage roll-off. Note the short channel effects degrade due to quantum tunneling, especially in the gate length of below 10nm, and DGMOSFETs have to be very strictly designed in the regime of below 10nm gate length since quantum tunneling becomes the main transport mechanism in the subthreshold region.

Performance enhancement and reduction of short channel effects of nano-MOSFET by using graded channel engineering

Abstract: The effect of the structure on electrical parameters of short channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors (DG MOSFETs) has been explored. To quantitatively assess the nanoscale DG MOSFET's characteristics, the On current(I on ), Off current (I off ), Sub threshold Swing (SS), Threshold voltage (V th ), and Drain-Induced Barrier Lowering (DIBL) are numerically calculated for the device with different channel length (L). Based on our two dimensional simulation, it is found that, to get optimum device characteristics and suppress short channel effects (SCEs) of nanoscale DG MOSFETs, t si and t ox should be simultaneously scaled down with respect to L. Even if it gives good results for V th , the device suffers for high DIBL, SS and I off . To suppress further these parameters, channel engineering technique is used followed by reducing the doping concentration of Source and Drain(S/D). The parameter extraction and simulation have been done by using the commercially available device simulation software ATLAS.

A novel implantless MOS thin-film transistor with simple processing, excellent performance and ambipolar operation capability

Abstract: A novel thin-film transistor (TFT) device that requires no implant step and is capable of ambipolar operation is proposed and successfully demonstrated The new structure features an undoped Si active channel, a tap metal field-plate (ie, the sub-gate), and Schottky source/drain The equivalent circuit of the device is given During device operation, a high fixed voltage is applied to the sub-gate to form a field-induced source/drain layer under the sub-gate region Depending on the polarity of the sub-gate bias, the device can be set for n-channel operation with positive sub-gate bias, and p-channel operation with negative sub-gate bias The new device is similar to conventional Schottky barrier (SB) MOSFET devices, with the exception of a field-induced source/drain region between the channel and Schottky source/drain The existence of the field-induced source/drain region serves to supply abundant channel carriers during on-state, while reducing the notorious off-state leakage that has plagued all previous SB MOSFETs The new device is also similar to MOSFETs with field-induced drain (FID), except that the heavily-doped source/drain region is replaced by Schottky source/drain While retaining all the advantages of FID such as low off-state leakage and low junction leakage, the use of Schottky source/drain not only reduces processing steps (ie, implant and annealing), but also allows ambipolar operation, thus greatly simplify processing steps especially for CMOS process integration

Anomalous drain current in n-MOSFET's and its suppression by deep ion implantation

Abstract: Effects of the deep ion implantation on the characteristics of the short channel n-MOSFET have been investigated by two-dimensional numerical analysis and verified experimentally. By the analysis, it has been found that the anomalous drain current which flows in the relatively deep region between the source and the drain has been effectively suppressed by the deep ion implantation of acceptor impurities into the channel region. Structure of short channel n-MOSFET with deep ion-implanted layer has been optimized by computer simulation to suppress the anomalous drain current. Experimentally, the low and steep subthreshold current characteristics have been obtained by deep ion implantation for short channel n-MOSFETs with L EFF = 1.2µm. Furthermore, the back gate bias dependence of the threshold voltage of the implanted short channel device can be made almost likely to that of the unimplanted long channel device.