Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

Origin of the performances degradation of two-dimensional-based metal-oxide-semiconductor field effect transistors in the sub-10 nm regime: A first-principles study

Abstract: The impact of the scaling of the channel length on the performances of metal-oxide-semiconductor field effect transistors, based on two-dimensional (2D) channel materials, is theoretically investigated, using density functional theory combined with the non-equilibrium Green's function method. It is found that the scaling of the channel length below 10 nm leads to strong device performance degradations. Our simulations reveal that this degradation is essentially due to the tunneling current flowing between the source and the drain in these aggressively scaled devices. It is shown that this electron tunneling process is modulated by the effective mass of the 2D channel material, and sets the limit of the scaling in future transistor designs.

Reconsideration of effective MOSFET channel length extracted from channel resistance

Abstract: Effective channel length (L EFF ) for the MOSFET having both “halo” and “extension” in its channel is extracted using “channel resistance method” (CRM). It is found that LEFF is strongly affected by the halo dose and gate voltage. As the halo dose is decreased to zero, LEFF converge the reasonable value and that for the MOSFET having uniform channel is uniquely determined, even if various sample MOSFET sets are used. Taking this property into consideration we propose new channel length definition, which is constant and obeys the classical current equation for the MOSFET with uniform channel, in order to provide the common channel length interpretation for both design and technology engineers.

Elimination of the gate and drain bias stresses in I–V characteristics of WSe2 FETs by using dual channel pulse measurement

Abstract: Intrinsic transfer and output characteristics of WSe2 field effect transistors are obtained by adopting the dual channel pulsed I–V measurement. Due to the DC gate bias stress during the measurement, a large hysteresis is observed and increased with increasing the sweeping range of the gate bias in the transfer curves. In addition, as a drain bias increases, the drain bias stress during the measurement induces the threshold voltage shift. The output curves measured by a DC method are significantly affected by the drain bias sweeping direction and the previous measurement, which leads to a large error in the analysis. By using the dual channel pulsed I–V measurement with a short turn-on time (10−4 s), a long turn-off time (1 s), and a base voltage (gate and drain bias during turn-off time) of 0 V, hysteretic behaviors caused by the gate bias stress and threshold voltage shift due to the drain bias stress in transfer curves are eliminated. The effect of the drain bias sweeping direction and the previous mea...

Variable threshold voltage complementary MOSFET with SOI structure

Abstract: The dependency of threshold voltage on adjusted bias voltage is varied between an N-channel MOSFET and a P-channel MOSFET. A support substrate, an insulating layer disposed on the support substrate, and island-shaped first and second silicon layers separately formed on the insulating layer; a first MOSFET formed of a fully depleted SOI where a first channel part is formed in the first silicon layer; and a second MOSFET formed of a partially depleted SOI where a second channel part is formed in the second silicon layer, the second MOSFET configures a complementary MOSFET with the first MOSFET, are provided. The threshold voltage of the second MOSFET formed of the partially depleted SOI is hardly varied because of a neutral region disposed in the second channel part, even though bias voltage is applied to the support substrate to vary the threshold voltage of the first MOSFET formed of the fully depleted SOI.

Method of simulating a semiconductor MOSFET

Abstract: A method of simulating the voltage-current characteristics of a short channel metal-oxide-semiconductor field effect transistor (MOSFET) by connecting a series of incremental MOSFETs of different threshold voltages. The threshold voltages near the source and the drain are reduced due to charge sharing. The substrate of each reduced threshold voltage incremental MOSFET is connected to its source. The reduction in threshold voltage can be obtained by Schwartz-Christoffel transformation of the depletion layer edges of the charge sharing region. From these threshold voltages one can calculate the incremental channel conductances and the voltage drops.