Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

Si/Ge/GaAs as channel material in nanowire-FET structures for future semiconductor devices

Abstract: In nano-scaled devices, as the voltage is scaled down in order to achieve low power which further causes the threshold voltage also to be scaled in order to meet the performance requirements. However, reduction in threshold voltage leads to increased leakage power in short channel devices. Nanowire FET (NW-FET) is a possible alternative to minimize short channel effects in traditional MOS structure. In this paper we have justified the advantage of naowire FET over MOSFET by varying oxide thickness. Then we have seen the impact of channel length over characteristics of NW-FET with Si, Ge and GaAs as channel materials. With nanoHUB simulation, we found that, while reducing the channel length from 12 nm to 4 nm, the drain current and subthreshold swing (SS) at a very small Vg increases due to tunnelling effect. In NW-FET, the drain current is normalized by the circumference of the nanowire and the SS is defined as the inverse of the slope of log 10 Id vs Vg curve. We have also simulated and analyzed that the electron density at channel region while reducing the channel length.

A proper deep submicron MOSFET model (PDSMM) and its applications for delay modeling of CMOS inverters

Abstract: A new and simple proper deep submicron MOSFET model (PDSMM) is proposed to accurately describe deep submicron MOSFET I-V characteristics. The second-order effects of deep submicron metal-oxide semiconductor field effect transistors (MOSFETs) such as charge carrier velocity saturation and channel length modulation are included in the PDSMM. The PDSMM is the extension of Shockley-Sah MOSFET model and Shichman-Hodges MOSFET model taking the second-order effects into account. Propagation delays of a complementary metal-oxide semiconductor (CMOS) inverter are obtained by using the PDSMM and by considering input transition time, drain diffusion capacitance, output load capacitance and gate-drain coupling capacitance. Even in the extreme conditions, the calculated results of propagation delays of deep submicron CMOS inverters are accurate compared with SPICE results of BSIM3 model. This shows that the proposed PDSMM is suitable to accurately simulate deep submicron MOSFET I-V behaviors.

An Improved Large Signal Model for 0.1 μm AlGaN/GaN High Electron Mobility Transistors (HEMTs) Process and Its Applications in Practical Monolithic Microwave Integrated Circuit (MMIC) Design in W band.

Abstract: An improved empirical large signal model for 0.1 µm AlGaN/GaN high electron mobility transistor (HEMT) process is proposed in this paper. The short channel effect including the drain induced barrier lowering (DIBL) effect and channel length modulation has been considered for the accurate description of DC characteristics. In-house AlGaN/GaN HEMTs with a gate-length of 0.1 μm and different dimensions have been employed to validate the accuracy of the large signal model. Good agreement has been achieved between the simulated and measured S parameters, I-V characteristics and large signal performance at 28 GHz. Furthermore, a monolithic microwave integrated circuit (MMIC) power amplifier from 92 GHz to 96 GHz has been designed for validation of the proposed model. Results show that the improved large signal model can be used up to W band.

Negative resistance in the output characteristics of SOI MOSFETs

Abstract: Summary form only given. The output characteristics (I/sub DS/ vs. V/sub DS/) of thin-film SOI MOSFETs show a decrease in drain current for increasing drain-source voltage at high power densities. In addition, the pinch-off point is shifted for small channel length, an effect inconsistent with theory due to the suppression of the body effect in these transistors. In an investigation of these phenomena it was found that both the negative resistance and the movement of the pinch-off point arise from a degradation of mobility caused by local heating due to power dissipation in the channel. This is a result of the poor thermal conductivity of the buried oxide; a worst case is that of a thin-film transistor on a thick buried insulator. >

Current Saturation Mechanisms in Junction Field-Effect Transistors*

Abstract: Publisher Summary This chapter examines the current saturation mechanisms in junction field-effect transistors (JFET). A JFET is an active semiconductor triode in which the current is primarily carried by the majority carriers. An n -channel JFET consists of a lightly doped n -type channel sandwiched between two heavily doped p -type gate layers. The drain current flows parallel to the metallurgical gate junctions that are reversely biased. The reverse bias across the p-n junctions depletes free carriers from the channel and produces space-charge regions extending into the channel. Under the current saturation condition, the electric field along the channel near the drain is comparable to the field normal to the channel. This two-dimensional field distribution violates the gradual channel approximation that assumes negligible electric field along the direction of the channel. The finite channel model provides a path for current flow after saturation that avoids the difficulty in the depleted channel model. The chapter also states that space-charge-limited current is physically realizable in very short JFET structures that produce triode-like characteristics.