Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

Temperature dependent analytical model for current-voltage characteristics of AlGaN/GaN power HEMT

Abstract: A temperature dependent analytical model has been presented for AlGaN/GaN power high electron mobility transistor (HEMT) to predict the DC performance at elevated temperatures. In this model the effects of temperature on band gap energy, sheet carrier density, threshold voltage, carrier mobility, and saturation velocity are taken into consideration. Channel length modulation in the saturation region of operation and spontaneous and piezoelectric polarization induced charges at the AlGaN/GaN heterointerface are also included in this model. Temperature- and bias-dependent on-wafer current–voltage measurements from 300 K to 500 K were carried out to verify the developed model. DC measurements and model predictions are presented for an AlGaN/GaN power HEMT fabricated on SiC substrate. The developed model shows good agreement with the measured data for a wide range of temperatures.

Halo doping effects in submicron DI-LDD device design

Abstract: The design of DI-LDD submicron channel devices is investigated, specifically focusing on the halo optimization for punchthrough and threshold falloff protection. Two dimensional numerical analysis is used to demonstrate the tradeoff between breakdown voltage and improved short channel threshold falloff as the halo concentration is increased. For a given halo doping level, there is a maximum permitted drain voltage for each channel length which is limited by avalanche breakdown, drain induced threshold lowering and punch-through. A window of useful halo doses is established from 5\times10^{16} to about 8\times10^{17} below which there is no significant improvement of the device and above which there is an unacceptable level of device degradation. A maximum V ds versus channel length curve for the polysilicon gate DI-LDD MOSFET is obtained which implies that power supply voltage must be scaled by approximately the same factor as channel length for this type of device.

Unified MOSFET model

Abstract: We present a basic analytical MOSFET model which describes both the below and above threshold regimes of device operation. The description is based on a charge control model which uses one unified expression for the effective differential channel capacitance. The model also accounts for series drain and source resistances, velocity saturation in the channel, finite output conductance in the saturation regime, and for the threshold voltage shift due to drain bias induced lowering of the injection barrier between the source and the channel (DIBL). The model parameters, such as the effective channel mobility, the saturation velocity, the source and drain resistances, etc. are extractable from experimental data. The model has been incorporated into our simulator, AIM-Spice. We apply the characterization procedure based on this model to a MOSFET with a quarter micron gate length and obtain excellent agreement with experimental data.

Partially depleted SOI MOSFETs under uniaxial tensile strain

Abstract: The effects of tensile uniaxial strain on the DC performance of partially-depleted silicon-on-insulator n and p-channel MOSFETs as a function of orientation and gate length are reported. The drain current of the n-MOSFETs increases for both longitudinal and transverse strain orientations with respect to the current flow direction. In the n-MOSFET, longitudinal strain provides greater enhancement than transverse strain. In contrast, for p-MOSFETs, longitudinal strain decreases the current while transverse strain increases the drain current. The magnitude of the fractional change in drain current decreases as gate length is reduced from 20 to 0.35 /spl mu/m. These phenomena are consistent with those of bulk silicon MOSFETs and are shown to be qualitatively correlated with the piezoresistance coefficients of the Si inversion layer. Analysis of the linear drain current versus gate voltage characteristics shows that the threshold voltage is independent of strain while the change in drain current tracks with the change in effective electron and hole mobility. Closer examination shows that as the gate length is reduced from 20 to 0.35 /spl mu/m, the relative increase in low-field electron and hole mobility is constant for transverse strain and generally decreases with gate length for longitudinal strain.

Modeling of amorphous-silicon thin-film transistors for circuit simulations with SPICE

Abstract: A static and dynamic model for amorphous silicon thin-film transistors is presented. The theory is based on an assumed exponential distribution of the deep states and the tail states in the energy gap. Expressions are derived that link the density of the localized states and the temperature to the drain current and the distribution of the charge in the transistor channel. In addition the authors take into account parasitic effects such as channel length modulation, off-resistance, drain and source resistances, mobile and free charges in the insulator, surface states, and overlap capacitances. The model is incorporated into the circuit simulation program SPICE. Charge conservation problems are overcome by using a charge-oriented dynamic transistor model. Simulated and measured current-voltage characteristics agree well. A 96-b gate line driver for addressing liquid-crystal displays, which was successfully designed and optimized with the model, is introduced. >