Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

Circuit for synchronous rectification with minimal reverse recovery losses

Abstract: A circuit for synchronous rectification including two power MOSFET transistor switches in which the bottom switch is a P channel MOSFET, rather than an N channel MOSFET. The circuit of the present invention uses a single channel driver, rather than a dual driver and eliminates the deadtime associated with conventional circuits, thus minimizing reverse recovery losses. In an alternative arrangement, the position of the output filter is switched so that the N channel MOSFET conducts during the freewheeling time and the P channel MOSFET (with a larger RDSON) conducts during the conductor charge cycle.

MOSFET with short channel structure and formation method thereof

Abstract: A MOSFET with a short channel structure and manufacturing processes for the same are described. The MOSFET has a substrate, a channel region, a source/drain region, a gate dielectric layer and a conductive layer. The channel region in the substrate includes a first region and a second region, in which the first region has a first threshold voltage and the second region has a second threshold voltage, respectively. The first threshold voltage is smaller than the second threshold voltage. The first threshold voltage of the first region can also be adjusted to reduce or increase effectively the resistance of the MOSFET when the MOSFET is turned on or off. Additionally, the first region has a shallower junction depth than that of the normal source/drain extension.

Drain-induced barrier lowering effect and its dependence on the channel doping in 4H-SiC MESFETs

Abstract: The drain-induced barrier lowering (DIBL) effect and its dependence on the channel doping concentration in 4H-SiC metal semiconductor field effect transistors (MESFETs) have been studied using the physical drift and diffusion model Our simulation results showed that the high drain voltage typically applied in 4H-SiC power MESFETs could drastically increase the threshold voltage when the ratio of the gate length to channel thickness (L/sub g//a) is less than 3 Larger channel doping concentration has also been found to enhance the DIBL effect, particularly at small L/sub g//a ratio In order to minimize the DIBL effect, the ratio of L/sub g//a should be kept greater than 3 for practical 4H-SiC MESFETs, especially when the channel doping is more than 5/spl times/10/sup 17/ cm/sup -3/

A study of second saturation effect of OPTVLD NMOS

Abstract: A detail analysis of the mechanism of output characteristic of OPTimized Variation Lateral Doping (OPTVLD) N-type MOS is presented in this paper. While a first current saturation of channel current is caused by the parasitic Junction FET (JFET), a second saturation is found in the state of high level drain current-voltage, which is explained by the enhancement of drain current with the increasing of drain voltage at high gate voltage due to that the carriers introduced by current modulate the electric field and cause intense impact ionization effect. It is expected that the analysis presented here can be used to improve the output characteristic of OPTVLD NMOS.