Topic
Channel length modulation
About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.
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15 Nov 2011
TL;DR: In this article, the authors developed a simple and accurate delay model for any UDSM CMOS inverter, NAND2 and NOR2 based on nth power law of MOSFET model when the channel length is of the order of less than or equal to 90nm.
Abstract: In this paper, we have developed a simple and accurate delay model for any Ultra Deep Sub-micron (UDSM) CMOS inverter, NAND2 & NOR2 based on nth power law of MOSFET model when the channel length is of the order of less than or equal to 90nm. We have taken all the parameters from BSIM.4.6.1 manual. This work derives analytical expression for the delay model of a CMOS inverter including all sorts of secondary effects such as Body Bias effect, Channel Length Modulation Effect (CLM), Velocity Saturation effect, Drain Induced Barrier Lowering (DIBL), etc which may occur in the Ultra Deep Submicron MOS devices. We also extend our delay model for 2 input CMOS NAND and NOR gate. Our result is better than nth power law and Cadence (UMC90nm) simulation result with respect to both quality and estimation time. Our proposed model gives an average error of only 3.63% with compare to Cadence Simulation result.
7 citations
TL;DR: In this paper, a vertical double-gate metal-oxide-semiconductor field effect transistor (DG MOSFET) with a standing-up ultrathin channel and self-aligned source and drain (S/D) is proposed.
Abstract: A fabrication technique for a vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) with a standing-up ultrathin channel (UTC) and self-aligned source and drain (S/D) is proposed. A 20nm thick vertical UTC with low channel thickness fluctuation was formed on a (110)-oriented Si substrate using orientation-dependent wet etching. The top and bottom S/D were self-aligned to the DGs by using a combination of ion implantation and solid-phase diffusion. The fabricated vertical DG MOSFETs revealed that the channel thickness less influences the threshold voltage. Furthermore, a low sub-threshold slope of 68.8mV/decade was achieved with a channel thickness of 20nm.
7 citations
30 May 1999
TL;DR: An error-neutralised switched-current comparator, which makes use of cross-coupled capacitors to compensate conductance errors resulting from both the overlap capacitances and the channel length modulation effect in the comparator's memory stage, which provides improved resolution with virtually no penalty on speed and power dissipation.
Abstract: This paper describes an error-neutralised switched-current comparator, which makes use of cross-coupled capacitors to compensate conductance errors resulting from both the overlap capacitances and the channel length modulation effect in the comparator's memory stage. The technique provides improved resolution with virtually no penalty on speed and power dissipation. Monte-Carlo simulations indicate a reliable resolution of over 8.5-bits with an improvement of more than 2.5-bits over that of the basic compensated SI comparator, at a comparison rate of over 100 MHz and power consumption of less than 0.85 mW.
7 citations
TL;DR: A 4T low-power linear output current-mediated CMOS APS imager, in which reset and read-out operations are carried-out simultaneously on two pixels of the same row, which greatly simplifies the pixel architecture.
Abstract: In this paper, we present a 4T low-power linear output current-mediated CMOS APS imager, in which reset and read-out operations are carried-out simultaneously on two pixels of the same row. The proposed operating technique greatly simplifies the pixel architecture with only four transistors and two control signals required, while six transistors and four control lines are required by its current-mediated counterpart. The imager achieves fixed pattern noise (FPN) correction during pixel-readout and exhibits a power consumption which is independent of the imager array size, since only a single current source is solicited at any given time due to the array-level operating technique. A linearization circuit technique using the transistor's channel length modulation effect is employed enabling to double the linear range of the pixel's photon-to-output signal transfer function. Performance analysis and experimental results are presented for a 32 × 32 image sensor array prototype, fabricated using AMS 0.35-μm process. The pixel size is 6.5 × 6.5 μm2 with 22% fill-factor. The chip total power consumption is less than 1 mW, at 50 frames/s with a 3.3 V power supply.
7 citations
TL;DR: In this article, the authors investigated the dependence of NBIS upon channel length, in amorphous-indium-gallium-zincoxide (a-IGZO) thin-film transistors (TFTs).
Abstract: We have investigated the dependence of Negative-Bias-illumination-Stress (NBIS) upon channel length, in amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). The negative shift of the transfer characteristic associated with NBIS decreases for increasing channel length and is practically suppressed in devices with L = 100-μm. The effect is consistent with creation of donor defects, mainly in the channel regions adjacent to source and drain contacts. Excellent agreement with experiment has been obtained by an analytical treatment, approximating the distribution of donors in the active layer by a double exponential with characteristic length LD ∼ Ln ∼ 10-μm, the latter being the electron diffusion length. The model also shows that a device with a non-uniform doping distribution along the active layer is in all equivalent, at low drain voltages, to a device with the same doping averaged over the active layer length. These results highlight a new aspect of the NBIS mechanism, that is, the ...
7 citations