Topic
Channel length modulation
About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.
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TL;DR: The difference in MOSFET threshold voltages caused by the difference in the extraction method is studied by measuring and analyzing its dependencies on channel length, substrate voltage and drain voltage.
Abstract: The difference in MOSFET threshold voltages caused by the difference in the extraction method is studied, by measuring and analyzing its dependencies on channel length, substrate voltage and drain voltage. It is found that the standard deviation of the difference between threshold voltages caused by the difference in the extraction method is less than that of the threshold voltage itself in a wafer. The dependencies of the threshold voltage on channel length, extracted from the drain current data around the threshold voltage, however, show different behavior from those extracted from the drain current data only in the subthreshold region or only in the ON region. It is considered that “channel-length modulation” causes this different behavior and, therefore, that those extraction methods are not desirable.
78 citations
Patent•
26 Aug 1991TL;DR: In this article, a silicon MOSFET with an effective channel length of under one micrometer without incurring severe short-channel effects is provided, which includes first and second channel regions located between the source and drain regions.
Abstract: A silicon MOSFET is provided, which can be made with an effective channel length of under one micrometer without incurring severe short-channel effects. The MOSFET includes first and second channel regions located between the source and drain regions, the first channel region overlaying the second channel region. The second channel region has a higher carrier density than the first channel region, and functions as a buried ground plane.
77 citations
Patent•
20 Oct 2003TL;DR: In this article, a threshold voltage adjusted long-channel transistor fabricated according to short channel transistor processes is described, which includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source-and drain regions.
Abstract: A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at least a part of the channel region with a gate formed over the gate oxide. The gate further includes at least one implant aperture formed therein with the channel region of the substrate further including an implanted region within the channel between the source and drain regions. Methods for forming the threshold voltage adjusted transistor are also disclosed.
76 citations
IBM1
TL;DR: In this paper, an effective channel length/external resistance extraction algorithm for MOSFET's is assessed by exercising the algorithm with currentvoltage data generated by two-dimensional numerical device simulation; the extracted quantities are directly compared to their known counterparts as they exist in the cross section of the simulated device.
Abstract: The accuracy of an effective channel length/external resistance extraction algorithm for MOSFET's is assessed. This is accomplished by exercising the algorithm with current-voltage data generated by two-dimensional numerical device simulation; the extracted quantities are directly compared to their known counterparts as they exist in the cross section of the simulated device. Extracted effective channel length is found to be within 0.07 µm of the metallurgical channel length in both the conventional and LDD MOSFET's studied here. Extracted external resistance is found to be a reasonable first-order estimate of actual device resistance external to the metallurgical channel but is unable to supply proper information regarding the gate bias dependence of this quantity.
74 citations
IBM1
TL;DR: In this article, a comprehensive investigation into the various mechanisms that limit the accuracy of channel length extraction techniques for lightly doped drain (LDD) MOSFET's is presented.
Abstract: A comprehensive investigation into the various mechanisms that limit the accuracy of channel length extraction techniques for lightly doped drain (LDD) MOSFET's is presented. Analytic equations are derived to quantify the sensitivity of the extraction techniques to the geometry effect, and bias dependence of the n-source and drain resistance. The analytic approach is supplemented and verified by exercising channel length extraction algorithms on current-voltage characteristics obtained from rigorous numerical simulations of a variety of LDD MOSFET's. The analyses clearly show that low gate overdrives and consistent threshold voltage measurements are required to accurately extract the metallurgical channel length. The analytic equations can be used to project the limitations of channel length extraction methods for future submicrometer LDD MOSFET's.
74 citations