Topic
Channel length modulation
About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.
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10 Feb 1978TL;DR: In this article, the authors propose to select a tail current that is sufficiently small to operate a long-tailed MOSFET pair such that their source-to-gate voltages are in the sub-threshold region.
Abstract: Long-tailed pair connections of MOSFET's are used as voltage comparators, the input stages of operational amplifiers, and other circuitry where their nearly infinite gate impedances can reduce the loading upon preceding circuitry. As conventionally operated, the tail current caused to flow through the interconnected source electrodes of the MOSFET's is sufficient to bias them such that their source-to-gate voltages exceed a threshold voltage, and the input voltage offset error of the long-tailed MOSFET pair is likely to be higher than that of most long-tailed bipolar transistor pairs. By selecting a tail current that is sufficiently small to operate a long-tailed MOSFET pair such that their source-to-gate voltages are in the sub-threshold region, the MOSFET's exhibit exponential drain current versus source-to-gate characteristics which result in markedly reduced input offset voltage error.
6 citations
01 Oct 2008
TL;DR: The paper describes NMOS and PMOS translinear cell which multiplies the current signals and which can be used for the current-mode signal processing and presents results of measurements on real structure composed using discrete transistors.
Abstract: The paper describes NMOS and PMOS translinear cell which multiplies the current signals and which can be used for the current-mode signal processing. The translinear cell consists of NMOS or PMOS transistors that are treated in the sub-threshold conduction region. In this region the transistors exhibit an exponential dependency of the drain current versus the gate voltage and thus the translinear principle can be used for description of the functionality. Operation region of the cell is limited by the validity of the exponential dependency and also by the transistors leakage currents. Significant error is also induced by the auxiliary current mirrors which are biasing the cells. Channel length modulation effect causes error of the input signals and thus the output signal is affected by the multiplicative error. The paper presents basic idea of the multiplying cell, presents results of simulations in CADENCE and also presents results of measurements on real structure composed using discrete transistors.
6 citations
19 Mar 2007
TL;DR: In this article, a continuous matching model with only two parameters is given, which is obtained by analyzing impact of short channel effects on matching degradation, and it is shown that the model is not satisfactory when discontinuities are observed.
Abstract: MOS transistor threshold voltage matching is usually modeled proportionally to reverse square root of gate area. Yet this model is not satisfactory when discontinuities are observed. In this paper, a continuous matching model with only two parameters is given. It is obtained by analyzing impact of short channel effects on matching degradation.
6 citations
TL;DR: In this article, the effective channel length and gate oxide thickness of poly-Si MOSFETs were measured using a simple CV technique, and the results of measurements on these devices are in agreement with literature.
Abstract: MOSFET's with variable channel lengths have been fabricated in both mono- and fine-grained polycrystalline silicon. We present a new method based upon a simple CV technique, to measure the effective channel length and gate oxide thickness. The channel-length reduction of the poly-Si MOSFET's was about 7.8 µm from which an effective lateral diffusion coefficient at 1000°C of phosphorus of 5 × 10-13cm2/s was calculated. The electron mobility was in the range of 10-20 cm2/V.s and the threshold voltage was about 17 V. The MOSFET's in mono-Si have been used as a reference. The results of measurements on these devices are in agreement with literature.
6 citations
TL;DR: In this article, the capacitance between source/drain and gate agrees with that of source and gate at the positive gate bias and the measured capacitance covers the whole channel area in addition to the source and drain overlap regions.
Abstract: Channel formation in In2O3/(Bi,La)4Ti3O12 ferroelectri-gate thin film transistors is discussed by means of capacitance-voltage characteristics. When the negative gate bias is applied, only the overlap regions are responsible for the capacitance, because the channel region is off and the source and drain regions are isolated. On the other hand, it is shown that the capacitance between source/drain and gate agrees with that of source and gate at the positive gate bias and that the measured capacitance covers the whole channel area in addition to the source and drain overlap regions.
6 citations