Topic
Channel length modulation
About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.
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TL;DR: In this article, the effect of channel length on hysteresis and threshold voltage shift in copper phthalocyanine (CuPc) based organic field effect transistors was studied.
5 citations
TL;DR: The 3D FinFETs deed provide the impressive gate controllability, especially in drive speed of transistors, but this advantage relatively brings some drawbacks in channel length modulation (CLM) causing the difficulty in device model establishment.
5 citations
13 Mar 2006
TL;DR: In this article, a simple and accurate method was presented for extraction of the effective gate resistance of RF MOSFETs, which can accurately predict not only the bias dependency but also the dependence on the number of fingers, channel lengths, and widths.
Abstract: A simple and accurate method is presented for extraction of the effective gate resistance of RF MOSFETs. Both the gate electrode resistance and the channel resistance were extracted separately. The proposed physics-based gate resistance model can accurately predict not only the bias dependency but also the dependence on the number of fingers, channel lengths, and widths.
5 citations
TL;DR: In this article, a drain current model for pre-and post-stress submicrometer buried-channel (BC) MOSFETs operated in the forward and reverse-biased modes was developed using the quasi-two-dimensional approach.
Abstract: In this paper, we report a new complete and analytical drain current model for pre- and post-stress submicrometer buried-channel (BC) MOSFETs operated in the forward- and reverse-biased modes. The model is valid in all regions of operation, and is developed using the quasi-two-dimensional approach. The hot-carrier-induced electron trapping in the oxide causes the channel shortening effect, which displays different behaviors for the device operated in the forward and reverse modes. It affects the threshold voltage reduction with channel length. This model incorporates the effects of velocity saturation, drain induced barrier lowering, channel length modulation, gate voltage induced mobility degradation, series source and drain resistances, and hot-carrier-induced oxide charges. The damaged channel region due to the fixed oxide charges trapped during hot-carrier injection is treated as a bias- and stress-time-dependent resistance. The resulting degraded BC MOSFET model is applicable for circuit simulation and its accuracy has been checked by the experimental data.
5 citations
TL;DR: In this article, a pseudo-silicon-on-insulator (P-SOI) MOSFET was developed for high device performance, comparable to those of a fully depleted (FD) SOI MOSFL.
Abstract: A pseudo-silicon-on-insulator (P-SOI) MOSFET fabricated using a bulk substrate has been developed for high device performance, comparable to those of a fully depleted (FD) SOI MOSFET, without problems caused by the usage of an SOI substrate. It features a p-n-p channel profile, in which a sandwiched thin n-type layer is fully depleted by the internal built-in potential. The thin n-type layer expands the depletion layer in the inversion state and reduces the vertical electric field at the MOS interface. As a result, the P-SOI MOSFET has a high drain-current drivability, a small subthreshold swing, and a low substrate-bias coefficient. A TiN gate electrode, which has a near midgap work function, is used to achieve optimum threshold voltage. It also increases the drain current by reducing the gate-electrode depletion. Counter doping to the buried p-type layer below the source and drain reduces junction capacitances. The subthreshold swing of the fabricated 0.25-/spl mu/m-gate-length P-SOI MOSFET becomes 73 mV/decade. Its drain current is 25% higher, substrate-bias coefficient is 40% lower, and source/drain junction capacitance is 60% lower, than those of a control MOSFET.
5 citations