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Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.


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Patent
03 Mar 1992
TL;DR: In this paper, the over current protection of an output MOS field effect transistor (FET) was discussed. And the degradation of the transistor was prevented by always limiting the abnormal over current of a load current IL even at the switching transient time of the output FET Q1.
Abstract: PURPOSE: To protect the over current destruction of an output MOS field effect transistor(FET). CONSTITUTION: A drain point voltage VD1 of an output MOSFET Q1 is compared with a drain point voltage VD2 of a reference MOSFET Q2 by a comparator 2 and in the case of VD1>VD2, a gate voltage VG is dropped by operating a gate bias voltage limit circuit 14 provided with an NPN transistor N for protection use and forward in-series diode SD corresponding to a compared output voltage V2 of the comparator 2. Thus, the destruction of the transistor is prevented by always limiting the abnormal over current of a load current IL even at the switching transient time of the output MOSFET Q1. COPYRIGHT: (C)1994,JPO&Japio

5 citations

Patent
05 May 1997
TL;DR: In this paper, a CMOS amplifier output stage including a complementary output MOSFET transistor pair whose channels are connected together in series between a supply voltage and a reference potential is presented.
Abstract: A CMOS amplifier output stage including a complementary output MOSFET transistor pair whose channels are connected together in series between a supply voltage and a reference potential, and whose gates are driven by a complementary MOSFET level shifting transistor pair and by bias voltage and current circuitry. Preferably, the level shifting transistor pair is a diode-connected NMOS transistor and a diode-connected PMOS transistor, the bias circuitry includes a source follower which drives the source of one of the diode-connected transistors with a current determined by an input voltage, all active elements of the invention are MOSFET transistors, and the minimum supply voltage required for operation is (V GS +2V SAT ), where V GS is the largest source to gate voltage of the MOSFET transistors and V SAT is the largest source to drain voltage of the MOSFET transistors during operation in the saturation region. This allows operation with a supply voltage as low as 1.8 volts with MOSFET transistors suitable for typical applications. The quiescent output current is well controlled and is determined by the device sizes of the MOSFET transistors. The invention can be implemented as part of a standard cell amplifier for any of a variety of mixed analog/digital circuits, even using high density, low voltage processes.

5 citations

Journal Article
TL;DR: In this article, the effect of threshold voltage on drain current for different channel lengths and analyses the impact of short channel on threshold voltage for Silicon n-MOS at room temperature were investigated.
Abstract: This paper investigates the effect of threshold voltage on drain current for different channel lengths and analyses the impact of short channel on threshold voltage for Silicon n-MOS at room temperature. For characterization, n-MOS model N08 is used where the short channel length and width of 0.8μm and 10μm and long channel length and width of 20μm and 200μm are chosen. The simulation is accomplished using LTSPICE and the data is analysed and characterized using MatLab. For both cases it is found a significant increase in drain current. Therefore, threshold voltage and channel length has substantial effect on drain current i.e. on device Id-Vds and Id-Vgs characteristics.

5 citations

Journal ArticleDOI
TL;DR: In this paper, the effects of self-heating and traps on the drain current transient responses of AlGaN/GaN HEMTs are studied by 2D numerical simulation, which indicates that accepter traps in the buffer are the major reason for the current collapse when the electric field significantly changes.
Abstract: The effects of self-heating and traps on the drain current transient responses of AlGaN/GaN HEMTs are studied by 2D numerical simulation. The variation of the drain current simulated by the drain turn-on pulses has been analyzed. Our results show that temperature is the main factor for the drain current lag. The time that the drain current takes to reach a steady state depends on the thermal time constant, which is 80 μs in this case. The dynamics of the trapping of electron and channel electron density under drain turn-on pulse voltage are discussed in detail, which indicates that the accepter traps in the buffer are the major reason for the current collapse when the electric field significantly changes. The channel electron density has been shown to increase as the channel temperature rises.

5 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202230
202111
202016
201915
20189