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Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.


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Journal ArticleDOI
TL;DR: In this paper, a drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: gm 1, gm 2, gm 3, and figure-of-merit (FOM) metrics; V IP2, V IP3, IIP3 and I-dB compression point, has been obtained.
Abstract: In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: gm 1 , gm 2 , gm 3 , and figure-of-merit (FOM) metrics; V IP2 , V IP3 , IIP3 and I-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth (X j ) or negative junction depth (NJD) have been examined for GME- TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.

5 citations

Journal ArticleDOI
TL;DR: This paper presents a new time-efficient modelling approach for UHF Dickson rectifiers that takes secondary effects, such as the body effect and short-channel effects into account resulting in a more accurate estimation of the generated output DC voltage and power conversion efficiency.
Abstract: This paper presents a new time-efficient modelling approach for UHF Dickson rectifiers. Due to the very low computation time, the approach can provide a quick and effective alternative to the standard transient simulations. The presented approach results in better estimation of the generated DC voltage and power conversion efficiency compared with the similar works in the literature. For the first time, an accurate mathematical relationship, including the non-zero reverse current, is expressed for finding the open load voltage of the Dickson rectifier while covering the broad range of RF amplitudes. The model uses the relation between the peak forward current and the load current to develop an input-to-output formula. Unlike the previous works, the channel length modulation is taken into consideration for the first time making the proposed model ideal for UHF Dickson rectifiers implemented with submicron CMOS transistors. Moreover, the proposed model takes secondary effects, such as the body effect and short-channel effects into account resulting in a more accurate estimation of the generated output DC voltage. Using the presented approach, a Dickson rectifier working at 900 MHz is implemented in a 0.18 µm CMOS process. Good agreement between simulation results, predicted results, and measurement results is observed.

5 citations

Patent
28 Mar 1996
TL;DR: In this paper, a p-channel interlocking transistor circuit with an additional circuit of regulating (20) and sensing (21) transistors was proposed, where the gate-source voltage (5) of the reference transistor, e.g., operating in saturation, was applied between the supply voltage and the regulating drain node.
Abstract: The circuit has several p-channel interlocking transistors including a reference transistor (1), an output transistor (2), and an additional circuit of regulating (20) and sensing (21) transistors. The sources of the outlet and reference transistors are coupled to a supply voltage (3) and both their gates are connected (9) to the drain (8) of the regulating transistor and the input current of a reference source (4). The additional transistors have respective channel widths (W1,W2) and channel lengths (L1,L2). The gate-source voltage (5) of the reference transistor, e.g. operating in saturation, is applied between the supply voltage and the regulating drain node (8). The gates of the additional transistors are connected (22) and coupled to the drain of the sensing transistor and to a bias current source (25) via a node (23). The sources of the additional transistors are respectively connected (10,11) to the drains of the reference and output transistors. The output transistor drain is also coupled to earth via a load resistor. The bias current is small and the ratio of the bias current to the reference current is equal to (w2/L2)/(W1/L1).

5 citations

Patent
20 Dec 2006
TL;DR: In this article, a tensile stress in the direction of flow direction of the drain current in the channel forming region of an n channel FET is greater than a transverse tensile pressure in the directions of flow of a drain current of a p-channel FET in a second region of the main surface of a semiconductor substrate.
Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.

5 citations

Journal ArticleDOI
TL;DR: In this article, a simple experimental technique is described for measuring the effective channel length and the surface-channel drift mobility in the insulated-gate field effect transistor (FET) made in 8 Ω cm silicon.
Abstract: A simple experimental technique is described for measuring the effective channel length and the surface-channel drift mobility in the insulated-gate field-effect transistor. Experimental results are presented for p channel transistors made in 8 Ω cm silicon.

5 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202230
202111
202016
201915
20189