Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

Nonuniform displacement of MOSFET channel pinchoff

Abstract: The effects of fixed positive oxide charge under the gate on the characteristics of MOSFET devices are well known The combined effects, however, of the oxide charge in the field and of the edge contour and impurity profile on the device characteristics have not been as extensively investigated in the past In this paper we address this problem and show results which give a new insight in the performance of MOSFET devices With the help of two- and three-dimensional numerical solutions of Poisson's equation, it was found that this oxide charge lowers the threshold potential resulting in an increase in conductivity towards the two edges of the channel along the width direction As a consequence, the geometric channel pinchoff locus shifts towards the drain as the channel edge is approached This is in contrast to the conventional assumption of the pinchoff locus being in parallel to the drain The oxide charge and the net impurity profile under the field region adjacent to the channel causes the current density to increase gradually towards the edges of the channel in channel width direction At high power densities, this may lead to drain-induced corner breakdown Further, in the subthreshold region of device operation, the electric field at the corner of the drain junction is increased, leading possibly to corner breakdown

Mosfet current limiting circuit, linear voltage regulator and voltage converting circuit

Abstract: A MOSFET current limiting circuit, a linear voltage regulator, and a voltage converting circuit are provided. A current limiting value of the MOSFET is adjusted with the temperature or the voltage drop across the drain and the source of the MOSFET. Accordingly, it is ensured that the MOSFET operates in the safe operating area in any situation. Therefore, the MOSFET is prevented from being burnt out, and the reliability thereof is also increased.

Effect of source/drain overlap region on device performance in a‐IGZO thin‐film transistors

Abstract: — In this paper, the effect of source/drain overlap length on the amorphous indium gallium zinc oxide (a-IGZO) TFT performance has been investigated. Results of this paper show that as source/drain overlap length decreases to a negative value forming S/D offset, the threshold voltage and S parameters of a-IGZO TFTs increased and the field-effect mobility decreased. The VT variation increases sharply as the channel length decreases because of the large resistance Roffset when it is formed at a-IGZO source/drain. In the experiment, Roffset of each 1 μm, evaluated from the transfer length method (TLM), shows approximately 54–66 kΩ. This means thatthe source/drain overlap length is a very important control parameter for uniform device characteristics of a-IGZO TFTs.

Investigation of multi-layered-gate electrode workfunction engineered recessed channel (MLGEWE-RC) sub-50 nm MOSFET: A novel design

Abstract: In this paper, a two-dimensional (2D) analytical sub-threshold model for a novel sub-50 nm multi-layered-gate electrode workfunction engineered recessed channel (MLGEWE-RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO2-based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain-induced barrier lowering, sub-threshold drain current and sub-threshold swing. Results reveal that MLGEWE-RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high-speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.