Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

Three-Dimensional Computational Analysis of Accumulated Body MOSFETs

Abstract: Accumulated body approach for short- and narrow-channel (10-nm scale) bulk Si MOSFETs is analyzed through 3-D finite-element studies. Accumulation of the side interfaces is achieved by a side-gate structure surrounding the body of the transistor, which leads to the accumulation of the body for narrow structures. A separately controlled top gate is used for transistor action. The simulation results show the suppression of leakage currents by 106 times for no side-interface charges, and by 1010 times for an interface positive fixed charge density of 1012 cm−2. The threshold voltage (VT ) can be dynamically increased by over 1 V with the accumulation of the body ( $V_{{\rm side}} = 0$ to −3 V) for W × $L = 10$ -nm × 15-nm structures, enabling electrostatic VT control and reliable high-temperature (>600 K) operation. Improvements in subthreshold slope and drain-induced barrier lowering are significant for narrower channel devices.

Semiconductor device composed of MOSFET having threshold voltage control section

Abstract: A semiconductor device includes a MOSFET which has a source and drain region of a first conductivity type, and an ion implanted channel section, and a pair of threshold control sections having a second conductivity type, one being disposed in a substrate surface between the channel section and the source region and the other being disposed in the substrate surface between the channel section and the drain region, and each of the threshold control sections having an impurity concentration so high that a threshold voltage of the MOSFET can be controlled. The threshold voltage of the MOSFET is not determined by the impurity concentration in the ion implanted channel section but is determined by the impurity concentration in the threshold voltage control sections. This enables the adequate control of the threshold voltage of the MOSFET that is part of a MOS integrated circuit and the simplification of the manufacturing method of the MOS integrated circuit.

Ultra-wideband complementary metal-oxide semiconductor low noise amplifier using CS-CG noise-cancellation and dual resonance network techniques

Abstract: In this paper, a low power ultra-wideband (UWB) low noise amplifier (LNA) with high and flat voltage gain is proposed using CS-CG noise-cancellation and dual resonance network techniques based on TSMC 180 nm technology. The CS-CG noise cancellation technique reduced the noise figure in 3-10.6 GHz frequency band, and the dual resonance network technique is applied to reach an acceptable input matching. In order to reduce the number of inductors, the active inductor is used in the noise cancellation stage. Also, to control voltage gain and input return loss, a resistor is connected in parallel to channel length modulation resistance of the transistor in the first stage. The developed LNA circuit provides a high and flat voltage gain of 12.75 dB with 0.65 dB variation, which is the result of using two stages common-source topology. An average noise figure of 2 dB, with its maximum value of 2.3 dB, an IIP3 of -8 dBm are obtained from 3 to 10.6 GHz, respectively. The obtained input and output matching value are better than -10 dB. The layout of proposed LNA occupies an area of 0.55 mm2 including ring pad and this structure consumes 11.56 mW from 1-V dc supply.

A 4T Low-Power Linear-Output Current-Mediated

Abstract: In this paper, we present a 4T low-power linear- output current-mediated CMOS APS imager, in which reset and read-out operations are carried-out simultaneously on two pixels of the same row. The proposed operating technique greatly simplifies the pixel architecture with only four transistors and two control signals required, while six transistors andfour control lines are required by its current-mediated counterpart. The imager achieves fixed pattern noise (FPN) correction during pixel-readout and exhibits a power consumption which is independent of the imager array size, since only a single current source is solicited at any given time due to the array-level operating technique. A linearization circuit technique using the transistor's channel length modulation effect is employed enabling to double the linear range of the pixel's photon-to-output signal transfer function. Performance analysis and experimental results are presented for a 32 32 image sensor array prototype, fabricated using AMS 0.35- m process. The pixel size is 6.5 6.5 m with 22% fill-factor. The chip total power consumption is less than 1 mW, at 50 frames/s with a 3.3 V power supply.

Electrical gate length measurement test structure for short channel MOSFET characteristics evaluation

Abstract: The electrical characteristics and gate lengths of individual MOSFETs are evaluated by a test structure with a Kelvin pattern as the gate electrode. The gate length measurement by SEM can be substituted by the electrical measurement using this test structure. Excellent correspondence is obtained between the threshold voltage lowering in the short channel region and the electrically measured gate length. Furthermore, the precision of drain-to-gate overlap length is improved by applying the effective channel length extraction method to the electrically measured gate length instead of the commonly used designed gate length.