Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

Analysis of Nanoscale Strained-Si/SiGe MOSFETs including Source/Drain Series Resistance through a Multi-iterative Technique

Abstract: As one of the important technological boosters, strain in Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) was first introduced in the 90 nm node and it has been continuing since then. Incorporating strain in MOSFETs allow us to increase the performance of the device without appreciable scaling of the devices. However, the presence of Source(S)/Drain(D) series resistance may degrade the performance of strained MOSFETs in the nanometer regime. Theoretical research emphasizing on the modeling and analysis of the drain current and threshold voltage of nanoscale strained MOSFETs (NSM) needs to incorporate the S/D series resistance in order to get a better insight of such devices. In this paper we have carried out a systematic analysis of drain current and threshold voltage of nanoscale strained Si/SiGe MOSFETs through a multi-iterative technique taking into account the effects of S/D series resistance. Our analysis has been further extended to study the impact of some important parameters such as strained Si layer thickness, gate oxide thickness, Ge mole fraction, and so on, on the electrical parameters of NSMs. The scaling trend of some device parameters have been modeled by analytical expressions obtained through curve-fitting technique and have been incorporated in our analysis to obtain optimized performance of NSMs.

Comparison of the scaling characteristics of nanoscale silicon N-channel multiple-gate MOSFETs

Abstract: This paper compares the scaling characteristics of the three leading multi-gate MOSFET designs, namely the finFET, trigate and omega-gate. A commercial numerical device simulator is employed using a common set of material parameters, device physics models and performance metrics. Examined initially are the short channel effects including the subthreshold slope S and drain induced barrier lowering DIBL as the gate length is scaled down to 20 nm. Subsequently investigated and compared are the effects of scaling of the fin body's width and height, the oxide thickness and the channel doping. The results suggest that the omega-gate MOSFET shows the best device scaling characteristics

Transition from partial to full depletion in advanced SOI MOSFETs: Impact of channel length and temperature

Abstract: This paper presents a detailed investigation of short-channel effects in advanced partially depleted SOI NMOSFETs. The influence of the back-gate voltage on the threshold voltage reveals the increase of the coupling effect with the channel length. The channel length impact is reversed by using pocket implants. Then SOI devices from the same wafer can behave as fully or partially depleted according to the channel length. This effective doping mechanism is amplified at low temperature operation. Systematic measurements show that long channel transistors become fully depleted before short channels, in particular when decreasing the temperature. The reduction of the channel length or the increase of the back-gate voltage and temperature attenuate the gate-induced floating body effect.

Adaptive in-rush current control for minimizing MOSFET peak temperature upon voltage step

Abstract: In one embodiment, a pass MOSFET is coupled in series between an input voltage and a load, and a bypass capacitor is connected in parallel with the load. In response to a voltage step across the MOSFET, the MOSFET is adaptively controlled to conduct an in-rush current of 2I CL =2I L during the bypass capacitor 12 charging time, where I CL is the capacitive current and I L is the load current. This optimizes the in-rush current to achieve a minimum peak temperature of the MOSFET. In one embodiment, a ramp capacitor connected to the drain of the MOSFET is part of a feedback path that tracks the MOSFET drain voltage to control the gate voltage.