Topic
Channel length modulation
About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.
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TL;DR: In this article, a 600-V vertical power MOSFET with low on-resistance is described, achieving near-ideal drain junction breakdown voltage and reduced drain spreading resistance from the use of an extended channel design.
Abstract: A 600-V vertical power MOSFET with low on-resistance is described. The low resistance is achieved by means of achieving near-ideal drain junction breakdown voltage and reduced drain spreading resistance from the use of an extended channel design. The various tradeoffs inherent in the design are discussed. Both calculated and experimental data are presented. The remote source configuration of the experimental device is also discussed.
45 citations
TL;DR: In this article, the degradation of 1- mu m-gate-length nMOSFET operating under normal biasing conditions at room temperature is analyzed and a physical model of hot-electron trapping in SiO/sub 2/ is developed and used with a two-dimensional device simulator (PISCES) to simulate the aging of the device.
Abstract: An analysis of the degradation of 1- mu m-gate-length nMOSFET operating under normal biasing conditions at room temperature is reported. A physical model of hot-electron trapping in SiO/sub 2/ is developed and is used with a two-dimensional device simulator (PISCES) to simulate the aging of the device under normal biasing conditions. The initial degradation takes place near the high-field drain region and spreads over a long time toward the source. The degraded I-V characteristics of the MOSFET exhibit a shift of the pinchoff voltage and a compression of the transconductance, for forward and reverse operation, respectively. The simulated degradation qualitatively agrees with reported experimental data. Large shifts of the MOSFET threshold voltage for small drain voltages result as the degradation is spreading toward the source. An inflection point arises for low gate and drain voltages in the drain I-V characteristics of the MOSFET. This inflection point originates when the pinchoff of the channel-induced trapped-electron charge is overcome by the drain voltage; the drain acts as a second gate (short-channel effect). The estimation of the device's lifetime by simulated aging is proposed. >
45 citations
01 Jan 1981
TL;DR: In this paper, an n-channel MOS process has been optimized to yield desirable characteristics for submicron channel length MOSFETs, including long-channel subthreshold characteristics, saturation drain characteristics up to 5V, and minimized substrate bias effects for transistors with channel lengths as small as 0.5µ.
Abstract: An n-channel MOS process has been optimized to yield desirable characteristics for submicron channel length MOSFETs. Process/device simulation is extensively used to find an optimized processing sequence compatible to typical production line processes. The simulation results show an excellent agreement to experimental data. We have obtained long-channel subthreshold characteristics, saturation drain characteristics up to 5V, and minimized substrate bias effects for transistors with channel lengths as small as 0.5µ. The short channel effects have been also minimized. A unique self-aligned silicidation technology which has been developed to reduce the increased resistance of down-scaled junctions is also presented.
45 citations
Patent•
IBM1
TL;DR: In this paper, a method for fabricating insulated gate field effect transistors with very short effective channel lengths was proposed, where the source and drain regions of the device are opened and self-aligned with the gate in one masking step and the drain region is then masked and the source side is implanted to adjust the threshold voltage of the high threshold voltage channel region.
Abstract: A method, including a sequence of process steps, for fabricating insulated gate field effect transistors having very short effective channel lengths. In a first version of the method, the source and drain regions of the device are opened in one process step and self-alignment of the source and the drain to the gate is achieved in one masking step. The drain region is then masked and the source side of the channel is implanted to adjust the threshold voltage of the high threshold voltage channel region. In a second version of the method, the source region is opened and self-aligned with the gate prior to the opening of drain region. Implantation to adjust the threshold voltage of the high threshold voltage channel region takes place before the drain region is opened, and then the drain region is opened and self-aligned with the gate in a further masking step. In either version, the threshold voltage is adjustable and the channel length is controlled to be a small value.
45 citations
TL;DR: In this paper, an analytic model for short-channel MOSFETs made of 2-D semiconductor material is presented, where a subthreshold current model is formulated based on the solutions to 2D Poisson's equation with negligible mobile charge.
Abstract: This paper presents an analytic $I$ – $V$ model for short-channel MOSFETs made of 2-D semiconductor material. First, a subthreshold current model is formulated based on the solutions to 2-D Poisson’s equation with negligible mobile charge. Next, a velocity saturation model is developed under the framework of a drift and diffusion long-channel model. These two models are then unified into an all region, short-channel $I$ – $V$ model with both drain induced barrier lowering and velocity saturation effects. Ballistic currents, including the intraband tunneling and the above-the-barrier transport, have been examined and compared with the thermionic currents.
43 citations