Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

MOSFET-Like Behavior of a-InGaZnO Thin-Film Transistors With Plasma-Exposed Source–Drain Bulk Region

Abstract: In this paper, we analyzed electrical characteristics of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) with plasma-exposed source-drain (S/D) bulk region. The parasitic resistance and effective channel length characteristics exhibit similar behavior with that of crystalline silicon metal oxide-semiconductor field effect transistor (c-Si MOSFET) that has doped S/D bulk region. The transfer curves little changed with gate overlap variation, and the width-normalized parasitic resistance obtained from transmission line method was as low as 3 to 6 Omegamiddotcm. The effective channel length was shorter than the mask channel length and showed gate-to-source (VGS) voltage dependency that is frequently observed for lightly doped drain (LDD) MOSFET. Experimental and simulation results showed that the plasma exposure caused an LDD-like doping effect in the S/D bulk region by inducing oxygen vacancy in the a-IGZO layer.

Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process

Abstract: A sub-0.05 μm channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 μm channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.

Technology for nanoperiodic doping of a metal–oxide–semiconductor field-effect transistor channel using a self-forming wave-ordered structure

Abstract: A self-forming nanostructure—a wave-ordered structure with a controllable period (20–180 nm)—results from the off-normal bombardment of amorphous silicon layers by low-energy (~ 1–10 keV) nitrogen ions. The nanostructure has been modified by reactive-ion etching in plasma to form a periodic nanomask on the surface of the channel region of a metal–oxide–semiconductor field-effect transistor (MOSFET). Implantation of arsenic ions through the nanomask followed by the technological steps completing the fabrication of the MOSFET resulted in a periodically doped channel field-effect transistor (PDCFET), which can be considered as a chain of short-channel MOSFETs with a common gate. Having worse subthreshold characteristics, PDCFETs show greater drain current and transconductance than to MOSFETs without a periodically doped channel. This improvement in device performance is attributed to the fact that the channel length is cut by the length of high-conductivity doped areas in the channel and that the voltage is distributed between the areas, depressing the scaling rules for short-channel MOSFETs and allowing the channel to be less doped between the areas, thus keeping drift mobility high.

Thermal effects in n-channel enhancement MOSFET's operated at cryogenic temperatures

Abstract: Thermal effects in n-channel enhancement-mode MOSFET's operated at cryogenic temperatures are discussed. Device heating is identified as the cause of drain current transients and the origin of this phenomenon is considered. Experimental results are presented in which thermal effects are studied as functions of temperature for various gate and drain biases. Drain current is found to be a monitor of device temperature, From an understanding of the thermal behavior of devices, the channel electron mobility can be examined as a function of temperature and gate bias. The observed thermal effects are explained in terms of material and device properties. The implications for future low-temperature CMOS VLSI development are discussed.