Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

A physically based compact model of partially depleted SOI MOSFETs for analog circuit simulation

Abstract: In this paper, the Southampton Thermal AnaloGue (STAG) compact model for partially depleted (PD) silicon-on-insulator (SOI) MOSFETs is presented. The model uses a single expression to model the channel current, thereby ensuring continuous transition between all operating regions. Furthermore, care has been taken to ensure that this expression is also infinitely differentiable, resulting in smooth and continuous conductances and capacitances as well as higher order derivatives. Floating-body effects, which are particular to PD SOI and which are of concern to analog circuit designers in this technology, are well modeled. Small geometry effects such as channel length modulation (CLM), drain-induced barrier lowering (DIBL), charge sharing, and high field mobility effects have also been included. Self-heating (SH) effects are much more apparent in SOI devices than in equivalent bulk devices. These have been modeled in a consistent manner, and the implementation in SPICE3f5 gives the user an additional thermal node which allows internal device temperature rises to be monitored and also accommodates the modeling of coupled heating between separate devices. The model has been successfully used to simulate a variety of circuits which commonly cause problems with convergence. Due to its inherent robustness, the model can normally achieve convergence without recourse to the setting of initial nodal voltage estimates.

Optimum design of n + -n - double-diffused drain MOSFET to reduce hot-carrier emission

Abstract: Channel electric field reduction using an n+-n-double-diffused drain MOS transistor to suppress hot-carrier emission is investigated. The double-diffused structure consists of a deep low-concentration P region and a shallow high-concentration As region. The channel electric field strongly depends on such process and device parameters as the length of the n-diffusion region, drain junction depth, gate oxide thickness, gate length, applied voltage, and P implant energy. The optimum condition for a double-diffused structure is determined based on those parameter dependences of the channel electric field. The results of the optimum drain impurity profile to give the minimum channel electric field are obtained when the maximum lateral electric field is located at the boundary between the P region and the As region. The hot-carrier immunity of MOSFET and test circuits are improved by two orders of magnitude and one order of magnitude, respectively, under the optimum conditions.

Battery protection circuit employing active regulation of charge and discharge devices

Abstract: A battery protection circuit includes back-to-back connected metal-oxide-semiconductor field-effect transistors (MOSFETs). Detection circuitry detects whether the battery is in a normal charge condition, an overcharged condition, or an over-discharged condition, and for the overcharged and over-discharged conditions the circuitry asserts a corresponding enable signal. For each MOSFET, a corresponding gate voltage regulating circuit controls the gate voltage such that (i) when the corresponding enable signal is de-asserted, the gate voltage is sufficient to enable the MOSFET to strongly conduct current in either direction, and (ii) when the corresponding enable signal is asserted, the gate voltage is a function of the polarity of drain-to-source voltage of the MOSFET. For each MOSFET, the corresponding gate voltage regulating circuit prevents the MOSFET from conducting when the drain-to-source voltage has an undesired polarity, and allows the MOSFET to conduct when the drain-to-source voltage has a desired polarity. One MOSFET prevents the flow of charge current, and the other prevents the flow of discharge current. When either MOSFET is conducting, its drain-to-source voltage is prevented from achieving a value sufficient to forward bias a parasitic diode associated with the source and drain terminals of the MOSFET. Current of correct polarity flows through the source-to-drain channel of a MOSFET rather than through the parasitic diode during the overcharged and over-discharged conditions.

Impact of the channel thickness on the performance of ultrathin InGaAs channel MOSFET devices

Abstract: InGaAs channel MOSFET devices with a channel thickness down to 3nm were fabricated and systematically characterized. Thinner channels result in improved electrostatics, however, the mobility rapidly drops to 110 cm2/Vs for the 3nm thick channel which results in significant loss of the drive current. 10 nm was found to be the optimum channel thickness with 77 mV/dec sub-threshold swing (SS). To account for the band-mixing and nonparabolicity of the III-V systems, 8-bands k.p simulations were conducted to gain an accurate insight into the device operation. As also verified experimentally, simulations suggest that the accumulation capacitance value increases as the channel thickness decreases due to the variations in the inversion charge profile. Simulations suggest that the InP buffer response affects the effective mass of the carriers and reduces the mobility as the channel becomes thinner. Based on this work, InGaAs channel thicknesses of 5nm and below hit severe performance issues.