Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

A new type of tunnel-effect transistor employing internal field emission of schottky barrier junction

Abstract: A new type of tunnel-effect transistor, which has nearly the same structure as conventional metal-oxide-silicon field-effect transistors (MOSFET's) except for a Schottky barrier source contact and a low resistivity channel layer, has been proposed. The structure has the advantage of an easy fabrication process and is capable of submicron channel length without the short channel effect. In the proposed device the drain current is controlled by the gate bias through the tunnel injection of electrons at the Schottky barrier source contact. A 2-D device simulation has shown that this device can have a high transconductance of 138 mS/mm at a drain voltage of 2 V.

A high power MOSFET with a vertical drain electrode and a meshed gate structure

Abstract: A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor.

Static Performance of 20 A, 1200 V 4H-SiC Power MOSFETs at Temperatures of −187°C to 300°C

Abstract: Silicon carbide (4H-SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) have been attracting tremendous attention for high-power applications at a wide range of operating temperatures, owing to their normally-off characteristics, high-speed switching operation, avalanche capability, and low on-resistance. To optimize performance of 4H-SiC MOSFETs for various applications at different temperatures, it is important to understand the mechanisms of temperature dependence of the key parameters, such as on-resistance, threshold voltage, and metal–oxide–semiconductor (MOS) channel mobility. We report on the temperature dependence of the on-resistance of 20 A, 1200 V 4H-SiC power MOSFETs for temperatures ranging from −187°C to 300°C. The MOSFET showed normally-off characteristics throughout the entire experimental temperature range. Different temperature dependences of the total on-resistance in different temperature regimes have been observed. Due to the poor MOS channel mobility and the low free carrier concentration in the inversion channel of the 4H-SiC MOSFET, the MOS channel resistance is the dominant part of the total on-resistance. This was also found to be true in a 4H-SiC long-channel lateral MOSFET.

Zero-temperature-coefficient biasing point of partially depleted SOI MOSFET's

Abstract: Experimental and analytical results of the front gate bias (V/sub GS/) and the drain current (I/sub DS/) with the drain voltage (V/sub DS/) of partially depleted (PD) SOI MOSFET at the Zero-Temperature-Coefficient (ZTC) point over a very wide temperature range (25-300/spl deg/C) are presented. Two distinct ZTC points are identified, one in the linear region and the other is in the saturation region. Additionally, the analysis takes into consideration the body effects, and mobility degradation with applied front gate bias. The analysis results are in excellent agreement with the experimental results. >

Physics-based compact model for ultra-scaled FinFETs

Abstract: A physical and explicit compact model for lightly doped FinFETs is presented. This design-oriented model is valid for a large range of silicon Fin widths and lengths, using only a very few number of model parameters. The quantum mechanical effects (QMEs), which are very significant for thin Fins below 15 nm, are included in the model as a correction to the surface potential. A physics-based approach is also followed to model short-channel effects (roll-off), drain-induced barrier lowering (DIBL), subthreshold slope degradation, drain saturation voltage, velocity saturation, channel length modulation and carrier mobility degradation. The quasi-static model is then developed and accurately accounts for small-geometry effects as well. This compact model is accurate in all regions of operation, from weak to strong inversion and from linear to saturation regions. It has been implemented in the high-level language Verilog-A and exhibits an excellent numerical efficiency. Finally, comparisons of the model with 3D numerical simulations show a very good agreement making this model well-suited for advanced circuit simulations.