Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

A New Method to Determine Effective MOSFET Channel Length

Abstract: An accurate and convenient method to determine an effective MOSFET channel length is proposed. This method is based on a computer aided evaluation of an intrinsic MOSFET channel resistance without using special test devices. N-channel silicon-gate MOSFETs were fabricated, and the channel length and its range of device to device scatter were evaluated . To define an effective channel, a simple model of the source-drain (S-D) diffusion layer is proposed. This model shows that the expected transition layer resistance between the S-D diffusion layer and the inverted channel layer agrees with the experimental results. The accuracy of this method is also discussed. It is found to be better than 0.1 µm.

Organic Thin Film Transistors: Structures, Models, Materials, Fabrication, and Applications: A Review

Abstract: Organic thin film transistor (OTFT) based device modeling and circuit application is a rapidly emerging research area. Taking cognizance of this fact, our paper reviews various basic to advanced OTFT structures, their performance parameters, materials of individual OTFT layers, their molecular structures, OTFT charge transport phenomena, and fabrication techniques. The performance of p- and n-type conducting polymer and small molecule organic semiconductors are reviewed primarily in terms of field effect mobility, current on/off ratio, and operating voltage for various OTFT structures. Moreover, different organic/inorganic materials for realizing the dielectric layer, electrodes, and the substrate in an OTFT are analyzed. Some of the compact models that are essential for predicting and optimizing the device performance are described that takes into account the mobility enhancement factor and channel length modulation. A detailed study of the single gate, dual gate, vertical channel, and cylindrical gate O...

Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation

Abstract: We present a simulation-based analysis of device design at the 25 nm channel length generation. Double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's are considered. Dependencies of short-channel effects on channel thickness and ground-plane bias are illustrated. Two-dimensional field effects in the gate insulator (high k) and the buried insulator (low k) in single-gate SOI are studied.

Switching mechanism in single-layer molybdenum disulfide transistors: an insight into current flow across Schottky barriers.

Abstract: In this article, we study the properties of metal contacts to single-layer molybdenum disulfide (MoS2) crystals, revealing the nature of switching mechanism in MoS2 transistors. On investigating transistor behavior as contact length changes, we find that the contact resistivity for metal/MoS2 junctions is defined by contact area instead of contact width. The minimum gate dependent transfer length is ∼0.63 μm in the on-state for metal (Ti) contacted single-layer MoS2. These results reveal that MoS2 transistors are Schottky barrier transistors, where the on/off states are switched by the tuning of the Schottky barriers at contacts. The effective barrier heights for source and drain barriers are primarily controlled by gate and drain biases, respectively. We discuss the drain induced barrier narrowing effect for short channel devices, which may reduce the influence of large contact resistance for MoS2 Schottky barrier transistors at the channel length scaling limit.

A Sub-1-V, 10 ppm/ $^{\circ}$ C, Nanopower Voltage Reference Generator

Abstract: An extreme low power voltage reference generator operating with a supply voltage ranging from 0.9 to 4 V has been implemented in AMS 0.35-mum CMOS process. The maximum supply current measured at the maximum supply voltage and at 80degC is 70 nA. A temperature coefficient of 10 ppm/degC is achieved as the combined effect of 1) a perfect suppression of the temperature dependence of mobility; 2) the compensation of the channel length modulation effect on the temperature coefficient; and 3) the absence of the body effect. The power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than -53 and -42 dB, respectively. The occupied chip area is 0.045 mm2.