Topic
Channel length modulation
About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.
Papers published on a yearly basis
Papers
More filters
TL;DR: In this paper, a method for extracting transport parameters in short-channel FETs is presented in the context of the Lundstrom model for quasi-ballistic short channel FET, which is based on an analysis of the channel length dependence of apparent mobility and virtual-source velocity.
Abstract: A method for extracting transport parameters in short-channel FETs is presented in the context of the Lundstrom model for quasi-ballistic short-channel FETs. The parameters extracted from measured data are unidirectional thermal velocity, critical length, and mean free path at low and high drain biases. The method is based on an analysis of the channel length dependence of apparent mobility and virtual-source (VS) velocity, which are obtained by fitting the VS model to measured data. Data from (100)-oriented undoped-body extremely thin silicon-on-insulator FETs with neutral stress liners are used to validate the method. Since this method does not assume any theoretical knowledge of band structure parameters, it can be applied to short-channel FETs with any geometry, any channel material, and with unknown levels of channel stress.
37 citations
TL;DR: In this article, a comparison of the electrical characteristics of small geometry p-channel and n-channel MOSFET's with and without field implantation leads to the conclusion that the field implantations is the main cause of the narrow-channel-width effect on threshold voltage, threshold-voltage increase and drain current degradation.
Abstract: Electrical characteristics of small geometry p-channel and n-channel MOSFET's are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity-saturation effects. Theoretical results on threshold voltage, threshold-voltage shift by a substrate bias voltage, and drain current are in good agreement with the experimental results over wide ranges of channel lengths from 1 to 9 µm and channel widths from 2 to 14 µm. A comparison of the electrical characteristics of MOSFET's with and without field implantation leads to the conclusion that the field implantation is the main cause of the narrow-channel-width effect on threshold-voltage increase and drain-current degradation. The carrier-velocity-saturation effect starts to appear at the 3-µm channel length for the n-channel device and at 1 µm for the p-channel device under 5-V operation. According to the theoretical analysis of a 1-µm-channel inverter circuit, a CMOS inverter has superior noise immunity with 1.4 to 2.0 times larger driving-current capability in a load MOS device and requires 9 percent less area than a 1-µm n-channel enhancement/depletion inverter.
37 citations
TL;DR: In this article, a semi-empirical strong inversion currentvoltage (I-V) model for submicrometer n-channel MOSFETs is proposed, which is suitable for circuit simulation and rapid process characterization.
Abstract: A semiempirical strong inversion current-voltage (I-V) model for submicrometer n-channel MOSFETs which is suitable for circuit simulation and rapid process characterization is proposed. The model is based on a more accurate velocity-field relationship in the linear region and finite drain conductance due to the channel length modulation effect in the saturation region. The parameter extraction starts from the experimental determination of the MOSFET saturation current and saturation voltage by differentiating the output characteristics in a unified and unambiguous way. These results are used in order to systematically extract the device and process parameters such as the effective electron saturation velocity and mobility, drain and source series resistances, effective gate length and characteristic length for channel length modulation, and short-channel effects. The values agree well with other independent measurements. The results of experimental studies of wide n-MOSFETs with nominal gate length of 0.8, 1.0, and 1.2 mu m fabricated by an n-well CMOS process are reported. The calculated I-V characteristics using the extracted parameters show excellent agreement with the measurement results. >
37 citations
TL;DR: In this article, scaling effects on the electrical properties of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) were investigated.
37 citations
10 Dec 2000
TL;DR: In this article, the selective epitaxial growth process was used to suppress short channel effect, junction leakage current, and parasitic resistance in sub-100 nm MOSFETs.
Abstract: High performance sub-100 nm MOSFETs have been realized utilizing elevated source/drain technologies. By utilizing the selective epitaxial growth process, the suppression of short channel effect, junction leakage current, and parasitic resistance are realized. Moreover, the necessity of special technique for channel engineering in order not to increase the gate-to-source/drain capacitance is described when using elevated source/drain structures. A novel prohibition process of deposition on poly-Si gate electrodes for reducing gate depletion is also mentioned.
37 citations