Topic
Channel length modulation
About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.
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TL;DR: In this paper, an accurate and comprehensive comparison between DMOS and Trench technologies for IGBTs is performed using extensive two-dimensional numerical simulations and fundamental physical modeling. But the analysis performed here describes rigorously these phenomena and accounts for new physical effects such as the channel length modulation and PIN diode carrier dynamics.
Abstract: An accurate and comprehensive comparison between DMOS and Trench technologies for Insulated Gate Bipolar Transistors (IGBT) is presented. The study is performed using extensive two-dimensional numerical simulations and fundamental physical modeling. Various phenomena such as the influence of the channel density on the forward voltage drop and the effect of the channel mobility degradation on the on-state characteristics have been the object of controversial studies. The analysis performed here describes rigorously these phenomena and accounts for new physical effects such as the channel length modulation and PIN diode carrier dynamics. It is concluded that at relatively high voltage and high current densities (>100 A/cm/sup 2/) an optimally designed Trench IGBT results in significant theoretical advantages over its conventional DMOS variant, mainly due to an increased packing density, PIN diode effect, reduced latch-up current density and elimination of the JFET effect. >
37 citations
TL;DR: In this article, an analytical model for a lateral MOSFET that includes the effects of temperature variation in 6H-SiC poly-type has been developed, and a good agreement between the analytical model and the experimental data has been observed.
Abstract: The advantages of silicon carbide (SiC) over silicon are significant for high power and high temperature device applications. An analytical model for a lateral MOSFET that includes the effects of temperature variation in 6H-SiC poly-type has been developed. The model has also been used to study the device behavior in 4H-SiC at high ambient temperature. The model includes the effects of temperature on the threshold voltage, the carrier mobility, the body leakage current, and the drain and source contact region resistances. The MOSFET output characteristics and parameter values have been compared with previously measured experimental data. A good agreement between the analytical model and the experimental data has been observed. 6H-SiC material system provides enhanced device performance compared to 4H-SiC counterpart for lateral MOSFET.
37 citations
TL;DR: In this article, a model for the drain I-V characteristics is proposed and a related model incorporating conductivity modulation that predicts linear relationships between the substrate and the collection currents and the drain current in this region of operation.
Abstract: When a short-channel MOSFET is driven into the avalanche-induced breakdown region, the drain current increases rapidly and usually shows a snapback characteristic. Both the substrate current and the current collected by a nearby reverse-biased p-n junction also increases with increasing drain current in this region of operation. All of these effects are associated with minority-carrier injection from the source junction into the substrate. A model for the drain I-V characteristics is proposed. Also presented is a related model incorporating conductivity modulation that predicts linear relationships between the substrate and the collection currents and the drain current in this region of operation. Experimental results agree well with the models.
37 citations
TL;DR: In this article, the behavior of radio frequency (RF) CMOS noise up to 24 GHz is analyzed and verified with measurements over a wide range of bias voltages and channel lengths.
Abstract: In this paper, the behavior of radio frequency (RF) CMOS noise up to 24 GHz is analyzed and verified with measurements over a wide range of bias voltages and channel lengths. For the first time, approaches for excess noise factor modeling are validated versus measurements. Furthermore, important RF CMOS figures of merit are examined over many CMOS generations. With the scaling of CMOS technology, optimum RF performance is shown to be shifted from higher moderate toward lower moderate inversion, providing important guidelines for RFIC design. The results are validated with the charge-based EKV3 compact model, which considers short-channel effects such as channel length modulation, velocity saturation, and carrier heating.
37 citations
TL;DR: In this paper, the authors demonstrate that by introducing a buried oxide in a bulk MOSFET only under the source and drain regions, i.e., using an oxygen implanted source/drain (OISD) structure, the drain capacitance can be made close to that of a silicon-on-insulator SOI MOSFLET while the self-heating effects are highly diminished.
Abstract: In this paper, we demonstrate that by introducing a buried oxide in a bulk MOSFET only under the source and drain regions, i.e., using an oxygen implanted source/drain (OISD) structure, the drain capacitance of a nanoscale MOSFET can be made close to that of a silicon-on-insulator SOI MOSFET while the self-heating effects are highly diminished and are similar to that of a bulk MOSFET. Two-dimensional simulation is used to optimize the length and thickness of the OISD regions.
37 citations