Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

A Novel Scaling Theory for Fully Depleted, Multiple-Gate MOSFET, Including Effective Number of Gates (ENGs)

Abstract: This brief presents a novel scaling theory for fully depleted, multiple-gate (MG) MOSFET. The scaling theory is derived from the equation for effective number of gates (ENGs), ENGQG=ENGDG,1+ENGDG,2 where the MG device can be genuinely broken into two equivalent double-gate (DG) transistors working in parallel based on the perimeter-weighted-sum method. Numerical device simulation data for drain-induced-barrier-lowering were compared with the model to validate the formula. Using the scaling theory, the minimum effective channel length improvement factor of ρMG=1-(ENGDG/ENGMG)1/2 shows an improvement of up to 30% in the minimum effective channel length for the MG MOSFET in comparison with DG MOSFET.

Novel intrinsic and extrinsic engineering for high-performance high-density self-aligned InGaAs MOSFETs: Precise channel thickness control and sub-40-nm metal contacts

Abstract: We have fabricated self-aligned tight-pitch InGaAs Quantum-well MOSFETs (QW-MOSFETs) with scaled channel thickness (t c ) and metal contact length (L c ) by a novel fabrication process that features precise dimensional control. Impact of t c scaling on transport, resistance and short channel effects (SCE) has been studied. A thick channel is favorable for transport, and a mobility of 8800 cm2/V·s is obtained with t c =11 nm at N s =2.6×1012 cm−2. Also, a record g m,max of 3.1 mS/µm and R on of 190 Ω·µm are obtained in MOSFETs with t c =9 nm and gate length L g =80 nm. In contrast, a thin channel is beneficial for SCE control. In a device with t c =4 nm and L g =80 nm, S is 111 mV/dec at V ds = 0.5 V. For the first time, working front-end device structures with 40 nm long contacts and gate-to-gate pitch of 150 nm are demonstrated. A new method to study the resistance properties of nanoscale contacts is proposed. We derive a specific contact resistivity between the Mo contact metal and the n+ InGaAs cap of ρ=(8±2)×10−9 Ω·cm2. We also infer a metal-to-channel resistance of 70 Ω·µm for 40 nm long contacts.

Two-Dimensional Analytical Drain Current Model for Double-Gate MOSFET Incorporating Dielectric Pocket

Abstract: In this paper, a dielectric-pocket double-gate MOSFET is described for low-voltage low-power applications. A complete drain current model has been developed including the channel length modulation effect. The analytical results have been validated by comparing them with the simulation results using the ATLAS 3-D device simulator. This paper analyzes the impact of dielectric pillars on large-signal performance metrics in terms of linearity and digital performance. Due to high Ion/Ioff ratio, device gain, and extremely low value of intrinsic delay and power dissipation, the proposed design is a suitable candidate for low-voltage low-power digital and analog applications.

Modeling the anomalous threshold voltage behavior of submicrometer MOSFET's

Abstract: A simple yet accurate semi-empirical analytical model for simulating the anomalous threshold voltage behavior in submicrometer MOSFETs is reported. The increase in the threshold voltage with decreasing channel length has been modeled by assuming a bias-independent, but channel-length-dependent, fixed charge at the source and drain ends. The new model requires two extra parameters in addition to the usual short-channel threshold voltage model parameters. These two parameters represent the magnitude of the fixed charge and the length over which the charge is spread at the source and drain ends. The model shows excellent agreement with the experimental threshold voltage data (within 2%) for submicrometer devices with varying oxide thickness, junction depth, and channel doping concentration. >