Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

Physical mechanisms for short channel effects in polysilicon thin films transistors

Abstract: It is demonstrated that channel avalanched multiplication is the dominant mechanism giving rise to short-channel threshold shifts in n- and p-channel polysilicon thin-film transistors (TFTs) at moderate or high drain bias The effects are greater in nMOS TFTs than pMOS due to the higher ionization rates for electrons in comparison to holes At low drain bias, a charge sharing mechanism dominates and p-channel devices show greater threshold shifts Device design parameters such as gate oxide or active island thickness have little influence, and the most effective method for reducing the threshold shifts is to reduce the supply voltage When the supply voltage is scaled to maintain a fixed minimum threshold voltage, CMOS circuit speeds decrease at shorter gate lengths when a fixed capacitive load is driven, although in more complex circuits the speed improves >

Statistical variability study of random dopant fluctuation on gate-all-around inversion-mode silicon nanowire field-effect transistors

Abstract: Random dopant fluctuation effects of gate-all-around inversion-mode silicon nanowire field-effect transistors (FETs) with different diameters and extension lengths are investigated. The nanowire FETs with smaller diameter and longer extension length reduce average values and variations of subthreshold swing and drain-induced barrier lowering, thus improving short channel immunity. Relative variations of the drain currents increase as the diameter decreases because of decreased current drivability from narrower channel cross-sections. Absolute variations of the drain currents decrease critically as the extension length increases due to decreasing the number of arsenic dopants penetrating into the channel region. To understand variability origins of the drain currents, variations of source/drain series resistance and low-field mobility are investigated. All these two parameters affect the variations of the drain currents concurrently. The nanowire FETs having extension lengths sufficient to prevent dopant penetration into the channel regions and maintaining relatively large cross-sections are suggested to achieve suitable short channel immunity and small variations of the drain currents.

Performance of 5-nm a-IGZO TFTs With Various Channel Lengths and an Etch Stopper Manufactured by Back UV Exposure

Abstract: Stable and fast-switching thin-film transistors and circuits incorporating 5-nm-thick amorphous-InGaZnO (a-IGZO) active layers are demonstrated, and their dependence on channel length is studied. Turn-on voltage shifts in the positive gate voltage direction as the channel length increases. A low area density of defects in the bulk a-IGZO, which is ultrathin, results in good stability under positive bias stress, whereas interdiffusion of electrons/electron donors from the highly doped source and drain regions to the channel edges results in the dependence of turn-on voltage on channel length. Stable operation of an 11-stage ring oscillator is achieved with a propagation delay time of ~97 μs/stage due to reduced gate-to-drain overlap capacitance and parasitic resistances.

Gate capacitor stress reduction in CMOS/BICMOS circuit

Abstract: Method and apparatus for using a MOSFET having a thin gate oxide layer as a gate capacitor is provided. The method includes the steps of biasing at least one of a source and a drain of the MOSFET by applying a nonzero voltage to the source and the drain, and applying a voltage to a gate of the MOSFET. The voltage applied to the gate is greater than a voltage rating of the MOSFET but less than the sum of the voltage rating and the voltage applied to the source and the drain. The gate of the MOSFET may have a length that measures at least 150.0 nanometers and no more than 350.0 nanometers. The thin gate oxide layer may have a thickness that measures at least 2.00 nanometers and no more than 7.00 nanometers. The MOSFET may be constructed using CMOS technology or BiCMOS technology. Apparatuses implementing this method include a capacitor, a read channel for a hard disk drive, and an electrical circuit for amplification of a signal.

An accurate JFET/MESFET model for circuit analysis☆☆☆

Abstract: An accurate model for junction field-effect transistors (JFETs) and for Schottky barrier field-effect transistors (MESFETs) with micron and submicron dimensions is presented. The following effects are modeled: distributed channel charge, electrostatic drain feedback, drift velocity saturation, channel length modulation, substrate bias effect, subthreshold region effect, short-length and narrow-width effects, drain-source punch-through, variable capacitance effects, and temperature effects. It is primarily physical rather than empirical and only one set of parameters is needed to simulate devices of a particular technology. The model is intended for silicon devices, but the extension to devices in semiconducting III – V compounds and with insulating substrates is straightforward. The model is compared to experimental data.