Topic
Channel length modulation
About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.
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TL;DR: In this paper, a new "ratio" method for effective channel length and threshold voltage extraction in MOS transistors is proposed, which relies on the same function as that used in the well known shift and ratio procedure.
Abstract: A new 'ratio' method for effective channel length and threshold voltage extraction in MOS transistors is proposed. The method, which relies on the same function as that used in the well known shift and ratio procedure, enables the effective channel length and threshold voltage difference to be extracted from simple linear regression applied to a short versus long channel correlation plot of the function Y(V/sub g/)=I/sub d//spl radic/g/sub m/ (I/sub d/ being the drain current and g/sub m/ the transconductance). This method has successfully been applied to 0.18-0.1 /spl mu/m CMOS technologies.
31 citations
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TL;DR: In this paper, physics-based short-channel models of threshold voltage and subthreshold swing for undoped symmetric double-gate MOSFETs are presented, developed from analytical solutions of the two-dimensional Poisson equations in the channel region.
Abstract: Physics-based compact short-channel models of threshold voltage and subthreshold swing for undoped symmetric double-gate MOSFETs are presented, developed from analytical solutions of the two-dimensional Poisson equations in the channel region. These models accurately characterize the subthreshold and near-threshold regions of operation by appropriately including essential phenomena such as volume inversion and the dominance of mobile charges over fixed charges under threshold conditions. Explicit, analytical expressions are derived for a scale length, which results from an evanescent-mode analysis. These equations readily quantify the impact of silicon film thickness and gate oxide thickness on the minimum channel length and device characteristics and can be used as an efficient guideline for device designs. These newly developed models are exploited to make a comprehensive projection on the scaling limits of undoped double-gate MOSFETs. On the individual device level, model predictions indicate that the minimum channel length can be scaled beyond 10 nm for a turn-off behavior of S=100 mV/dec for a silicon film thickness below 5 nm and an electrical equivalent oxide thickness below 1 nm.
31 citations
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01 May 1995TL;DR: In this article, a high saturation current, low leakage, Fermi threshold field effect transistor with a predetermined minimum doping concentration of the source and drain facing the channel to maximize the saturation current of the transistor is presented.
Abstract: A high saturation current, low leakage, Fermi threshold field effect transistor includes a predetermined minimum doping concentration of the source and drain facing the channel to maximize the saturation current of the transistor Source and drain doping gradient regions between the source/drain and the channel, respectively, of thickness greater than 300Å are also provided The threshold voltage of the Fermi-FET may also be lowered from twice the Fermi potential of the substrate, while still maintaining zero static electric field in the channel perpendicular to the substrate, by increasing the doping concentration of the channel from that which produces a threshold voltage of twice the Fermi potential By maintaining a predetermined channel depth, preferably about 600Å, the saturation current and threshold voltage may be independently varied by increasing the source/drain doping concentration facing the channel and by increasing the excess carrier concentration in the channel, respectively A Fermi-FET having a gate insulator thickness of less than 120Å, and a channel length of less than about 1 μm can thereby provide a P-channel saturation current of at least 4 amperes per centimeter of channel width and an N-channel saturation current of at least 7 amperes per centimeter of channel width, with a leakage current of less than 10 picoamperes per micron of channel length using power supplies of between 0 and 5 volts
31 citations
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28 Jul 1972
TL;DR: The drain-current to drain-voltage characteristic simulates the anode-to-anode voltage characteristic of the triode vacuum tube very closely as mentioned in this paper, and the drain current will not flow where the drain voltage is below a certain threshold voltage, and will flow when the drain volage is above the threshold voltage exhibiting a linear resistance characteristic.
Abstract: A field effect transistor comprises a semiconductor channel, a source and a drain electrode formed at the opposite ends of the channel and a gate electrode provided on the side of the channel. The channel has a small impurity density and therefore the depletion layer extending from the gate goes deep into the channel to substantially close the conductive portion of the channel even in the absence of a gate voltage. The drain current will not flow where the drain voltage is below a certain threshold voltage, and will flow where the drain volage is above the threshold voltage exhibiting a linear resistance characteristic. This drain-current to drain-voltage characteristic simulates the anode-current to anode-voltage characteristic of the triode vacuum tube very closely.
30 citations
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03 Jun 1996TL;DR: In this article, the authors describe a manufacturing method for MOSFET devices that are free from reverse short channel effect usually found in such devices made by prior art processes, in contrast to the prior art process sequence, the channel implant is made after the source and drain already formed by implantation and its damage already annealed out.
Abstract: This invention describes a manufacturing method for MOSFET devices that are free from reverse short channel effect usually found in such devices made by prior art processes. In contrast to the prior art process sequence, the channel implant is made after the source and drain already formed by implantation and its damage already annealed out. The enhanced diffusion of the channel implant, caused by damage generated point defects and responsible for the reverse short channel effect, is therefore avoided. The channel implantation uses high energy ions to penetrate through the polysilicon gate, forming a threshold voltage adjustment and punch-through barrier layer under the gate. The channel implant through the source/drain regions is deeper than the source/drain junctions so that the junction capacitance is reduced in comparison with the prior art.
30 citations