Topic
Channel length modulation
About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.
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TL;DR: In this paper, a method for removing the discontinuity in G/sub ds/ going from the linear region to the saturation region in the MOS level 3 model of SPICE by modifying the channel length modulation expression is described.
Abstract: A method for removing the discontinuity in G/sub ds/ going from the linear region to the saturation region in the MOS level 3 model of SPICE by modifying the channel length modulation expression is described. A detailed analysis of the problem and simulation results before and after the modification are presented. >
28 citations
TL;DR: In this article, the authors proposed a novel nanoscale fully depleted silicon-on-insulator metal-oxide-semiconductor field effect transistor (SOI-MOSFET) with modified current mechanism for leakage current reduction.
28 citations
TL;DR: In this article, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage.
Abstract: Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (
28 citations
TL;DR: In this article, a simple technique to optimize the device parameters of the retrograde channel doping MOSFET to minimize short channel effects for a constant threshold voltage is presented, and the results indicate that the highest possible substrate doping does not necessarily result in minimum short-channel effects.
Abstract: A simple technique to optimize the device parameters of the retrograde channel doping MOSFET to minimize short channel effects for a constant threshold voltage is presented in this work. The results indicate that the highest possible substrate doping does not necessarily result in minimum short channel effects.
27 citations
01 Jan 2003
TL;DR: In this paper, the authors proposed SDOI MOSFET, which allows the source and drain region of a MOSFL to stay over an oxide layer while the channel region remains on bulk Silicon.
Abstract: We demonstrated a new process, SDOI, to achieve extremely low junction capacitance on bulk Silicon MOSFET. SDOI stands for Source Drain On Insulator. It allows the source and drain region of a MOSFET to stay over an oxide layer while the channel region remains on bulk Silicon. The junction capacitance reduction resulted in 18% improvement in ring oscillator speed on 0.13um transistors. The DC characteristics of SDOI MOSFET matches closely to that of bulk Silicon MOSFET. Unlike SOI MOSFET, SDOI MOSFET has no floating body effect. It does not require special device models and can be easily integrated with other bulk Silicon devices, such as diodes and bipolar transistors. We also investigated process factors that affect the yield and performance of SDOI MOSFET.
27 citations