Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

Threshold voltage controlled 0.1-/spl mu/m MOSFET utilizing inversion layer as extreme shallow source/drain

Abstract: MOSFETs containing sub-gates as sidewall spacers of the main gate are fabricated. The inversion layers induced in these MOSFETs by the sub-gates are used as source and drain, in order to investigate how the extremely shallow junction affects the short channel characteristics of MOSFETs. Significant improvement in the short channel characteristics is observed in comparison with conventional MOSFETs whose junctions are formed by ion implantation. These new MOSFETs do not show threshold voltage roll-off at the defined gate length around 0.1 /spl mu/m, and punchthrough is not observed down to 0.07 /spl mu/m. >

Vertical floating gate transistor with epitaxial channel

Abstract: A vertical floating gate transistor includes an epitaxially formed channel between its lower source/drain region and upper source/drain region, with a floating gate electrode in a trench that extends vertically through those regions and a control or programming gate electrode above and separated from the floating gate electrode. A process for forming the vertical floating gate transistor implants the substrate to provide the lower source/drain region, then forms an epitaxial layer that provides the channel over the previously formed lower source/drain region. Then, the upper source/drain region is implanted above the lower source/drain region and epitaxial channel layer, followed by formation of a vertical trench and the floating and control gates. Forming the epitaxial layer over a previously implanted lower source/drain region allows independent control of the resistivity of the lower source/drain region, such that it can have low resistivity, facilitating device symmetry. Also, the epitaxial channel layer has improved doping uniformity over diffusion type channel region, lowering channel length and increasing performance and yield. Finally, the source/drain regions may incorporate two separate dopants to provide an extended region that further minimizes the channel length while providing higher punch through voltage levels and retaining low resistivity.

Two-dimensional analytical model for drain induced barrier lowering (DIBL) in short channel MOSFETs

Abstract: An analytical model to elucidate various effects of drain induced barrier lowering in a short channel MOSFET's performance is presented. In particular, the amount of drain bias induced depletion charge under the gate is assessed and an expression for the distribution of this charge along the channel length is developed. Then, based on a simplified two-dimensional solution of Poisson's equation along the channel, the potential barrier lowering between source and channel, and consequently threshold voltage shift is estimated. The results are compared with numerical simulation data for deep submicron NMOS devices. Finally, the dependence of threshold voltage on drain bias for LDD and non-LDD MOSFETs with effective channel lengths down to deep submicron range has been investigated. Due to its simplicity, the developed model is suitable for circuit simulators.

Electrical Properties of Phase Change and Channel Current Control in Ultrathin Phase-Change Channel Transistor Memory by Annealing

Abstract: We studied phase-change channel transistor memory devices with an ultrathin Ge2Sb2Te5 chalcogenide film channel and tried to demonstrate two combined functions (memory: resistance change and selection: channel current control) by annealing in this paper. Drain–source resistance can be markedly decreased by 2 – 3 orders of magnitude after annealing due to the phase change from the amorphous to crystalline phases. A channel current control effect in which the drain current decreases with the gate voltage was clearly observed in 10- and 20-nm-thick Ge2Sb2Te5 devices. The absolute channel current modulation by the gate voltage in the crystalline state is much stronger than that in the amorphous state. Furthermore, the channel current control ability in devices with thin Ge2Sb2Te5 is stronger than that in devices with thick Ge2Sb2Te5. The channel current control effect might result from the potential change of the ultrathin Ge2Sb2Te5 channel by the gate voltage. [DOI: 10.1143/JJAP.45.3238]

Thin film transistor with a sub-gate structure and a drain offset region

Abstract: A novel structure of a polycrystalline silicon thin film transistor manifested in a drain offset region and a sub-gate structure. The drain offset region is formed between a channel region and a drain region in the polycrystalline silicon thin film. The sub-gate structure comprises at least one sub-gate, except for a main gate which is provided in a normal field effect transistor. This structure is applicable to either an upper gate type or a bottom gate type thin film transistor. The sub-gate structure may include an upper sub-gate and/or a bottom sub-gate. The upper sub-gate overlays the channel region, drain offset and drain regions through an insulation layer. The bottom sub-gate underlies the channel region, drain offset and drain regions through an insulation layer. The sub-gate is applied with the same voltage or less as the drain voltage thereby permitting a relaxation of a high field concentration caused at a drain junction to be realized. This may provide a reduction of a leakage current and a security of a high ON-current.