Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

Physical analysis for saturation behavior of hot-carrier degradation in lightly doped drain N-channel metal-oxide-semiconductor field effect transistors

Abstract: This paper experimentally demonstrates that hot carrier degradation curves of lightly doped drain n-channel metal-oxide-semiconductor field effect transistors (LDDNMOSFETs) has universal behavior even if different stress conditions were applied. From this phenomena, we have proved that the Φ it/E m, the ratio of critical barrier for interface state generation to the maximum electric field, doesn't change so that accurate lifetime prediction for drain avalanche hot carrier (DAHC) is possible using conventional log (τI d) vs log (I sub/I d) method even if the degradation vs stress time curves show a saturation behavior. We have modeled stressed LDD as an equivalent circuit which is comprised by a surface channel MOSFET and two buried channel MOSFETs. And various circuit simulations were done by mobility change of drain side buried channel MOSFET. As a result, a modified mobility model with a lower limit parameter for mobility degradation has been developed, which successfully describes the saturation behavior of device degradation.

Analytical Thermal Noise Model of Deep-submicron MOSFETs

Abstract: This paper presents an analytical noise model for the drain thermal noise, the induced gate noise, and their correlation coefficient in deep-submicron MOSFETs, which is valid in both linear region and saturation region. The impedance field method was used to calculate the external drain thermal noise current. The effect of channel length modulation was included in the analytical equation. The noise behavior of MOSFETs with decreasing channel length was successfully predicted from our model.

VDMOS Power Transistor Drain-Source Resistance Radiation Dependence

Abstract: Data on the effects of neutron and gamma radiation on the drain-source resistance characteristics of power VDMOS transistors are presented. The change in resistance with neutron exposure is related to the resistivity of the drain material, which in turn can be related to the drain-source breakdown voltage. A device with a 450-V rating experienced a factor of 13 increase in resistance on exposure to a neutron fluence of 1014/cm2 whereas one with a breakdown voltage of 150 V experiences no increase in resistance. Threshold voltage shifts of about 2 V occurred at a gamma dose of 105 rad(Si) without bias and was accelerated by positive gate bias. All of these data are consistent with the predictions of a simple model for the dependence of drain-source resistance on gate voltage and drain resistivity. This model illustrates a general separability of neutron and gamma effects on power VDMOS devices. The systems implications for using this type device in a radiation environment are briefly addressed.

A Compact Model of Subthreshold Current With Source/Drain Depletion Effect for the Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs

Abstract: In this paper, an analytical potential-based model in the subthreshold regime for short-channel junctionless cylindrical surrounding-gate MOSFETs is proposed as the source/drain depletion effect considered. The threshold voltage ( $V_{\textrm {th}}$ ), subthreshold slope, and drain-induced barrier lowering are also correspondingly derived, which give explicit explanations of the short-channel effects on junctionless MOSFETs in the subthreshold regime. The compact model is verified by the numerical simulation, and the results match well.

High performance sub-20-nm-channel-length extremely-thin body InAs-on-insulator tri-gate MOSFETs with high short channel effect immunity and V th tunability

Abstract: We have investigated the effects of vertical scaling and the tri-gate structure on electrical properties of extremely-thin-body (ETB) InAs-on-insulator (-OI) MOSFETs. It was found that body thickness (Tbody) scaling provides better SCEs control, whereas Tbody scaling causes the reduction of the mobility limited by channel thickness fluctuation (δTbody) scattering (μfluctuation). To achieve better SCEs control, the thickness of channel layer (Tchannel) scaling is more favorable than the thickness of MOS interface buffer layer (Tbuffer) scaling, indicating necessity of quantum well (QW) channel structure. Also, the Tri-gate ETB InAs-OI MOSFETs shows significant improvement of short channel effects (SCEs) control with small effective mobility (μeff) reduction. As a result, we have successfully fabricated sub-20-nm-Lch InAs-OI MOSFETs with good electrostatic with S.S. of 84 mV/dec, DIBL of 22 mV/V, and high transconductance (Gm) of 1.64 mS/um. Furthermore, we have demonstrated wide-range threshold voltage (Vth) tunability in Tri-gate InAs-OI MOSFETs through back bias voltage (VB) control.