Topic
Channel length modulation
About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.
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TL;DR: In this paper, the significance of various noise sources in field effect transistors is discussed, and a lower limit to the channel length is set by the carrier velocity saturation effects, which are the hot carrier channel noise and the gate leakage current due to impact ionization.
Abstract: In this paper the significance of various noise sources in field-effect transistors is discussed. The intrinsic thermal noise of the conducting channel can be reduced by reducing the channel length. A lower limit to the channel length is set by the carrier velocity saturation effects, which are the hot carrier channel noise and the gate leakage current due to impact ionization. Devices with a ratio of the transconductance to the input capacitance of 3 x 109 sec-1 have been made, and a further improvement appears to be possible.
23 citations
TL;DR: In this paper, a prototype of a field effect transistor (FET) based on the Mott metal-insulator transition (MIT) in vanadium dioxide was described and possible solutions to increase the efficiency of the VO2-based FET were analyzed and described.
Abstract: In this paper we describe a prototype of a field effect transistor (FET) based on the Mott metal–insulator transition (MIT) in vanadium dioxide. It has been shown that increasing the modulation of the channel resistance, the gain of the field effect, and an increase of the amplification factor can be achieved by lowering the temperature of the channel. An increase of the transistor amplification factor by more than twice is shown while reducing the temperature from RT down to −21 °C. It is also shown that the modulation of the channel resistance is not associated with the occurrence of dynamic current through the gate insulator and the VO2-channel. Possible solutions to increase the efficiency of the VO2-based FET are analyzed and described.
23 citations
08 Dec 2002
TL;DR: In this paper, the authors describe the improved characteristics of a newly proposed ultra-narrow channel floating-dot memory where the channel width is scaled to sub-10 nm, thanks to the classical bottleneck effect and the quantum confinement effect.
Abstract: This paper describes the improved characteristics of a newly proposed ultra-narrow channel floating-dot memory where the channel width is scaled to sub-10 nm. Thanks to the classical bottleneck effect and the quantum confinement effect, large threshold voltage shift and long retention time have been obtained in the fabricated ultra-narrow channel memory. The extreme case of the proposed ultra-narrow channel memory is the ultimate single-electron memory where one bit is represented by one electron. In the narrowest (5 nm) channel device, the threefold increase in drain current has been actually observed due to the discharging of a single electron from a dot.
23 citations
Patent•
03 May 1994TL;DR: In this article, a modulation doped field effect transistor (10) is formed to have a drain (28, 12, 11) that is vertically displaced from the source (16, 17) and channel (20, 21) regions.
Abstract: A modulation doped field effect transistor (10) is formed to have a drain (28, 12, 11) that is vertically displaced from the source (16, 17) and channel (20, 21) regions. The transistor (10) has the source (16, 17), channel (20, 21) and a portion of the drain (28) arranged laterally so that current (27) flows from the source (16, 17) laterally to the drain (28, 12, 11). A heterojunction layer (18) on the channel region (20, 21) facilitates forming a two dimensional electron gas in the channel (20, 21) region which provides the transistor (10) with a high transconductance.
23 citations
TL;DR: In this paper, a two-step reduction technique is proposed to estimate the performance of complex gates, where a complex gate is first mapped to an equivalent NAND gate form and then the NAND is mapped to a inverter macromodel.
Abstract: In this paper, a new efficient two-step reduction technique is proposed to estimate the performance of complex gates. A complex gate is first mapped to an equivalent NAND gate form and then the NAND gate is mapped to an inverter macromodel. Accurate reduction techniques for series-connected transistors precisely model effective transconductance, the channel length modulation effect, input terminal position dependence, parasitic capacitances, and the body effect. Adequate solutions to address these sources of delay errors, which may total 100% or more, have not been previously provided. These reduction techniques are not tied to a single macromodel, but generally are applicable to existing linear and nonlinear macromodels. Experiments with a wide range of input transitions and output loadings for various gates show nearly identical results between SPICE2 and the proposed techniques. The proposed macromodeling techniques are up to several hundred times faster than SPICE2 and up to several times faster than existing nonlinear macromodels for individual gates.
23 citations