Topic
Channel length modulation
About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.
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TL;DR: In this paper, an explicit single-piece MOSFET model is derived from a surface potential formulation, which covers small-geometry effects, like mobility reduction, channel-length modulation, carrier velocity saturation, and short and narrow-channel effects.
Abstract: An explicit single-piece MOSFET model is derived from a surface potential formulation. The model covers small-geometry effects, like mobility reduction, channel-length modulation, carrier velocity saturation, and short- and narrow-channel effects. Good agreement has been found with measured characteristics. Furthermore, the DC current calculated using the new model shows smooth transitions through all regions of operation. Therefore the convergence when employed in circuit simulation will be improved. >
21 citations
TL;DR: In this article, the authors discuss linear and nonlinear potential profiles in the meaning of the space-charge field generated by injected carriers, and the influence on currentvoltage relation used for mobility evaluation in linear and saturated regions is proposed as well as transition between these states.
Abstract: The gradual channel approximation is widely used for organic field-effect transistors with an assumption of linear potential profile across the channel. However, this is in contradiction with reported potential profiles. Here, we discuss linear and nonlinear potential profiles in the meaning of the space-charge field generated by injected carriers. The influence on current-voltage relation used for mobility evaluation in linear and saturated regions is proposed as well as transition between these states. In addition, the effect of the space-charge on the potential drop and field around the drain electrode in the saturation region is discussed.
21 citations
TL;DR: In this paper, a 0.5/spl mu/m-rule thin-film SOI power MOSFET was fabricated to evaluate its radio-frequency (RF) performance.
Abstract: A state-of-the-art 0.5-/spl mu/m-rule thin-film SOI power MOSFET was fabricated to evaluate its radio-frequency (RF) performance. The impact of the device structural parameters, such as channel length and drain offset length, on the RF performance of thin-film SOI power MOSFETs was also investigated. The fabricated device with channel length of 0.5 /spl mu/m and drain offset length of 0.4 /spl mu/m showed excellent performance. Its breakdown voltage was more than 10 V, which is sufficient for a lithium ion battery to be used as a power source. Its cutoff and maximum oscillation frequencies were 14.7 and 19 GHz, respectively. Its power-added efficiency at 2 GHz was 64%.
21 citations
Patent•
05 Aug 1998
TL;DR: In this paper, a method of forming a MOS transistor without a lightly doped drain (LDD) region between the channel region and drain is provided, where the tilted implantation forms a relatively short channel length, with respect to the length of the gate electrode.
Abstract: A method of forming a MOS transistor without a lightly doped drain (LDD) region between the channel region and drain is provided. The channel region is formed from a tilted ion implantation after the deposition of the gate oxide layer. The tilted implantation forms a relatively short channel length, with respect to the length of the gate electrode. The position of the channel is offset, and directly adjoins the source. The non-channel area under the gate, adjacent the drain, replaces the LDD region between the channel and the drain. This drain extension acts to more evenly distribute electric fields so that large breakdown voltages are possible. The small channel length, and eliminated LDD region adjacent the source, act to reduce resistance between the source and drain. In this manner, larger Id currents and faster switching speeds are obtained. A MOS transistor having a short, offset channel and drain extension is also provided.
21 citations
Patent•
12 Jan 2004
TL;DR: In this article, the authors proposed a gate turn of a MOSFET with a gate current that exceeds the drain current, suggesting a new geometry and packaging arrangement for the gate drive and gate turn.
Abstract: Usually, in power converters, the load on a MOSFET is inductive, and the current cannot change rapidly. The drain current is the upper limit of the Miller current, so that if the gate current is larger than the drain current, the gate capacitance will continue to discharge and there can be no Miller shelf. If a parallel capacitor is used with a MOSFET, once the drain voltage starts to rise, the load current divides, placing a new lower limit on the Miller current. To drive a MOSFET with a gate current that exceeds the drain current, the circuit impedances have to be very low, suggesting a new geometry and packaging arrangement for the MOSFET and gate drive. A compatible gate turn of circuit is also disclosed.
21 citations