Topic
Channel length modulation
About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.
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TL;DR: In this paper, the effect of systematic downscaling of MOS channel length on the performance of hybrid GaN MOS-HEMT with numerical simulations is quantitatively evaluated, and a specific on-resistance of 2.1mΩcm 2 has been projected for a MOS Channel length of 0.38μm.
Abstract: In this paper, we have studied the effect of systematic downscaling of MOS channel length of the performance of the hybrid GaN MOS-HEMT with numerical simulations. The improvement in on-state conduction, together with concomitant short channel effects, including drain induced barrier lowering (DIBL) is quantitatively evaluated. A specific on-resistance of 2.1 mΩ cm 2 has been projected for a MOS channel length of 0.38 μm. We also have assessed the impact of high- k gate dielectrics, such as Al 2 O 3 . In addition, we have found that adding a thin GaN cap layer on top of AlGaN barrier can help reducing short channel effects.
20 citations
TL;DR: In this article, a two dimensional (2D) rectangular recessed channel-silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE).
Abstract: In this paper a two dimensional (2D) rectangular recessed channel–silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed.
20 citations
05 Dec 1999
TL;DR: In this paper, the authors discuss drain architecture in relation to performance and the possibility of sub-0.1 /spl mu/m CMOS devices and find that an abrupt junction is indispensable for source/drain (S/D) extension to obtain higher drain current capability.
Abstract: The continued scaling of Si MOSFET faces many critical issues. In this paper, the authors discuss drain architecture in relation to performance and the possibility of sub-0.1 /spl mu/m CMOS devices. It is found that an abrupt junction is indispensable for source/drain (S/D) extension to obtain higher drain current capability. On the other hand, a graded junction is desirable for deep S/D to decrease the junction capacitance. The drain architecture combined with doping technology such as plasma doping and spike anneal is one of the most important solutions for sub-0.1 /spl mu/m MOSFETs.
19 citations
IBM1
TL;DR: In this paper, it was shown that the threshold voltage of a depletion-mode MOSFET is a function of its mode of operation (linear or saturated) due to a change in dominant conduction mechanisms caused by the finite depth of donor impurities in the channel.
Abstract: This paper presents the results of a study of the characteristics of the depletion-mode MOSFET. In particular, it is shown that the threshold voltage of this device is a function of its mode of operation (linear or saturated) due to a change in dominant conduction mechanisms caused by the finite depth of donor impurities in the channel. The effect of these impurities on the short channel behavior of the devices also is examined.
19 citations
TL;DR: In this article, the effects of short channel on double gate MOSFETs were studied and a self-consistent Poisson-Schrodinger solver in two dimensions over the entire device was used to evaluate the variation of the threshold voltage, the subthreshold slope, the leakage current and the drain-induced barrier lowering when channel length LCH decreases.
Abstract: In this paper, we study the effects of short channel on double gate MOSFETs. We evaluate the variation of the threshold voltage, the subthreshold slope, the leakage current and the drain-induced barrier lowering when channel length LCH decreases. Furthermore, quantum effects on the performance of DG-MOSFETs are addressed and discussed. We also study the influence of metal gate work function on the performance of nanoscale MOSFETs. We use a self-consistent Poisson-Schrodinger solver in two dimensions over the entire device. A good agreement with numerical simulation results is obtained.
19 citations