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Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.


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Journal ArticleDOI
TL;DR: In this article, an analytic I-V model for lightly doped drain (LDD) MOSFET devices is presented, in which the n-region is considered to be a modified buried-channel MOS-FET device, and the channel region is considered as an intrinsic enhancement-mode MOS FET device.
Abstract: An analytic I-V model for lightly doped drain (LDD) MOSFET devices is presented. In this model, the n-region is considered to be a modified buried-channel MOSFET device, and the channel region is considered to be an intrinsic enhancement-mode MOSFET device. Combining the models of these two regions, the drain current in the linear/saturation regions and the saturation voltage can be calculated directly from the terminal voltages. In addition, the parameters used in the channel region can be extracted by a series of least square fittings. According to comparisons between the experimental data measured from the test transistors and the theoretical calculations, the developed I-V model is shown to be valid for wide ranges of channel lengths.

19 citations

Journal ArticleDOI
TL;DR: In this paper, the authors performed a comprehensive scaling study of a carbon nanotube field effect transistor (CNTFET) with halo doping (HD) using self-consistent and atomistic scale simulations.

18 citations

Journal ArticleDOI
TL;DR: In this paper, an anomalous sub-threshold characteristic of the MOSFET for lowvoltage operation was reported, and the cause of channel length independent subthreshold characteristics was identified as the localized pileup of channel dopants near the source and drain ends of the channel.
Abstract: This work reports an anomalous subthreshold characteristic of the MOSFET for the first time. It is observed that the subthreshold characteristic does not change as the channel length decreases. The cause of channel length independent subthreshold characteristics is identified as the localized pileup of channel dopants near the source and drain ends of the channel. The low surface potential of this pileup region limits the subthreshold current of MOSFET. As a result, the ratio of on-current to off-current for this MOSFET increases as the channel length is reduced, which is an important parameter for low-voltage operation. It is found that a MOSFET with channel length independent subthreshold characteristic is more suitable for low-voltage operation.

18 citations

Journal ArticleDOI
TL;DR: A detailed analysis of nonequilibrium electron transport in n-type Si and In0.3Ga0.7As MOSFETs scaled into the ultimate limit of 5-nm gate length is carried out using ensemble Monte Carlo device simulations as discussed by the authors.
Abstract: A detailed analysis of nonequilibrium electron transport in n-type Si and In0.3Ga0.7As MOSFETs scaled into ultimate limit of 5-nm gate length is carried out using ensemble Monte Carlo device simulations. The analysis is based on simulations of ID-VG characteristics for a template, 25-nm gate length Si MOSFET compared against previous results from various Monte Carlo device codes, and for an equivalent 25-nm gate length In0.3Ga0.7As MOSFET. The transistors are then laterally scaled from a gate length of 25 nm to 20, 15, 10 and 5 nm monitoring the average electron velocity, energy, and sheet density along the channel at a supply voltage of 1.0 V. A degradation of the injection velocity with the scaling of a gate/channel length is observed. While we have found a decrease in the overall electron velocity profile along the Si channel for gate lengths smaller than 10 nm and a decrease in the injection velocity from a gate length of 20 nm, the increase in the intrinsic drain current in the scaling process is continuous thanks to the increasing velocity at the drain side. However, the velocity in the InGaAs channel MOSFETs increases steadily during the scaling but the increase in the intrinsic drain current is less pronounced. This is the result of a source starvation, due to a low density of states in III-V semiconductors, which cannot provide a large enough electron sheet density in the channel. This effect is partially mitigated by the enhancement of density of states as a proportion of electrons in the source/drain transfers to upper valleys with a larger electron effective mass.

18 citations

Journal ArticleDOI
TL;DR: In this article, a model that conserves charge, is valid in the strong inversion regime, and is based on the quasi-static approximation is presented, and major second-order effects such as carrier velocity saturation, mobility degradation, and channel-length modulation are included in the derivation of current and charges.
Abstract: A model that conserves charge, is valid in the strong inversion regime, and is based on the quasi-static approximation is presented. Major second-order effects such as carrier velocity saturation, mobility degradation, and channel-length modulation are included in the derivation of current and charges. The theoretical predictions of the model are compared to both experimental and numerically simulated data and are found to be in good agreement over a wide range of gate and drain voltages and to confirm many properties that have been observed or predicted. >

18 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202230
202111
202016
201915
20189