Topic
Channel length modulation
About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.
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TL;DR: The presented CP calibration technique compensates for the DC current mismatch and the mismatch due to channel length modulation effect and therefore improves the performance of CP-PLLs in nano-meter CMOS implementations.
18 citations
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03 May 2004TL;DR: In this article, the impact of non-rectangular channel geometry on the basic MOSFET parameters such as the drive and leakage current was examined, and the resulting inverter characteristics and of the static noise margin of an SRAM cell were derived.
Abstract: Deep sub-wavelength optical imaging distorts the shape of MOSFET channel on silicon due to proximity and refraction. As a result, channel area is no longer rectangular, i.e., represented by the single channel length and width (LxW) for device simulations, but by an L(W) distribution. This distribution would differ across the optical proximity correction (OPC) and photo process windows, possibly exceeding the typical 10% CD variation entitlement. While one can expect that the process-related L(W) would impact MOSFET electrical properties, its circuit consequences have not been
addressed in the typical simulation flow. In this work, we examine the impact of non-rectangular channel geometry on the basic MOSFET parameters such as the drive and leakage current. We then create models of the resulting inverter characteristics and of the static noise margin of an SRAM cell. In the process, we show how to simulate MOSFET gate shape for the different OPC and lithography options and identify the channel sections responsible for the parametric
variations. Finally, we calculate electrical characteristics of SRAM cell based on the discretized representation of individual MOSFETs, showing how the distortion of channel geometry would degrade cell performance.
18 citations
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TL;DR: In this article, a simple closed-form analytical expression of the threshold voltage for a narrow-width MOSFET was developed, which gives a threshold voltage expression as a function of gate oxide thickness and channel doping concentration.
Abstract: A simple closed-form analytical expression of the threshold voltage for a narrow-width MOSFET is developed. The narrow-width model gives a threshold voltage expression as a function of gate oxide thickness, channel doping concentration, backgate bias and channel width. The theory is compared with experimental results and the agreement is close.
18 citations
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TL;DR: In this paper, the influence of extremely shallow source and drain junctions on the short channel effects of Si MOSFET's is experimentally investigated, and two subgates formed as side-wall spacers of a main gate induce inversion layers which work as the virtual source or drain.
Abstract: The influence of extremely shallow source and drain junctions on the short channel effects of Si MOSFET's are experimentally investigated. These extremely shallow junctions are realized in MOSFET's with a triple-gate structure. Two subgates formed as side-wall spacers of a main gate induce inversion layers which work as the virtual source and drain. Significant improvement in threshold voltage roll-off and punchthrough characteristics are obtained in comparison with conventional MOSFET's whose junctions are formed by ion implantation: threshold voltage roll off is suppressed down to a physical gate length of 0.1 /spl mu/m while punchthrough is suppressed down to 0.07 /spl mu/m, the minimum pattern size delineated. It is also demonstrated experimentally that the carrier concentrations in the source and drain do not have any influence on the short channel effects. >
18 citations
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01 May 2005TL;DR: In this paper, the memory characteristics as a function of channel widths for different channel lengths are presented, and the results show that the Si-NCs memory is highly scalable in terms of the channel size.
Abstract: The use of nanoscale channel MOSFETs as a candidate for future nonvolatile memory is extensively investigated. The device consists of a wire channel MOSFET with nanometer dimensions on which Si nanocrystals (Si-NCs) are deposited. The memory characteristics as a function of the channel widths for different channel lengths are presented. The channel length dimensions are defined between 100-1000 nm by electron beam lithography and the width dimensions are reduced from a few tens of nanometers down to sub-5 nm by wet etching and thermal oxidation processes. It is found that the controllability of the fabrication process is enhanced as the channel length is reduced to 100 nm. Moreover, memory performances are improved with decreasing channel width due to the bottleneck effect. These results show that the Si-NCs memory is highly scalable in terms of the channel size. In the narrowest channel devices, i.e., in the sub-5-nm range, coulomb-blockade oscillations are obtained due to the ultra-small regions formed in the channel. In such devices, a strong enhancement of the retention characteristics has been found as a result of the quantum mechanical narrow channel effect in the ultra-narrow channel.
18 citations