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Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.


Papers
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Journal ArticleDOI
TL;DR: In this article, the authors present a new method which takes into account the effect of the lateral field to extract the deep submicrometre MOSFET parameters such as threshold voltage, effective channel length, effective mobility and parasitic series resistance.
Abstract: As the MOSFET channel length shrinks to 0.1 µm, the influence of the lateral field on the device characteristics becomes increasingly important even at low drain voltage (10 mV). The authors present a new method which takes into account the effect of the lateral field to extract the deep submicrometre MOSFET parameters such as threshold voltage, effective channel length, effective mobility and parasitic series resistance.

18 citations

Patent
10 Aug 1977
TL;DR: In this article, a stable temperature-insensitive constant reference voltage circuit is provided which can be implemented in either MOS or bipolar technology, where the circuit is implemented by MOSFET devices on a single chip with another circuit such as an A/D converter.
Abstract: A stable temperature-insensitive constant reference voltage circuit is provided which can be implemented in either MOS or bipolar technology The circuit may be implemented by MOSFET devices on a single chip with another circuit such as an A/D converter to provide a monolithic A/D converter with its own internal reference voltage circuit The reference voltage circuit consists of a series-connected long channel MOSFET and short channel MOSFET which produce, at their junction, a temperature-independent voltage A differential circuit containing three MOSFET devices is then provided with one of the devices serving as a current source which carries the current of the other two MOSFET devices which are in parallel The gates of the two parallel MOSFET devices are connected respectively to the junction between the long channel and short channel device and to the output voltage Current divides between the two parallel MOSFET devices in such a way as to cause a constant output voltage to be produced regardless of the variations of the supply voltage sources Vdd or Vgg The various MOSFET devices are formed on the same substrate containing the circuit components being connected to the constant stable voltage reference source

18 citations

Journal ArticleDOI
TL;DR: In this article, a bandgap engineering technique is proposed for the suppression of the short channel effect and its effectiveness is quantitatively calculated in the case of the SiGe source/drain structure with a device simulation.
Abstract: A bandgap engineering technique is proposed for the suppression of the short-channel effect (SCE) and its effectiveness is quantitatively calculated in the case of the SiGe source/drain structure with a device simulation. The drain-induced barrier lowering (DIBL) and the charge sharing are suppressed by the presence of the valence band discontinuity between the SiGe source/drain and Si channel. In order to obtain the full advantage of this structure, it is necessary to locate the SiGe layers both at the source/drain regions and the SiSe/Si interface at the pn junction or inside the channel region. The effectiveness increases with the increase of the valence band discontinuity (Ge concentration). As a result of the suppression of the SCE and the reduction of the minimum gate length, the drain current increases, and thus high-speed operation can be realized with this technique.

18 citations

Patent
04 Nov 1999
TL;DR: In this article, offset drain Fermi threshold field effect transistor (Fermi-FET) is introduced to introduce a drift region between the drain region and the FermI-Fet channel that can provide high voltage and/or high frequency FETs.
Abstract: An offset drain Fermi-threshold field effect transistor (Fermi-FET) includes spaced apart source and drain regions in an integrated circuit substrate, and a Fermi-FET channel in the integrated circuit substrate, between the spaced apart source and drain regions. A gate insulating layer is on the integrated circuit substrate between the spaced apart source and drain regions, and a gate electrode is on the gate insulating layer. The gate electrode is closer to the source region than to the drain region. Stated differently, the drain region is spaced farther away from the gate electrode than the source region. The offset drain Fermi-FET can introduce a drift region between the drain region and the Fermi-FET channel that can provide the high voltage and/or high frequency Fermi-FETs, while retaining the Fermi-FET advantages in the channel.

18 citations

Proceedings ArticleDOI
01 Dec 2014
TL;DR: In this article, a highly stable Al 2 O 3 gate oxide on a C-H bonded channel of diamond, high-temperature and highvoltage metal-oxide-semiconductor field effect transistor (MOSFET) has been realized.
Abstract: By forming a highly stable Al 2 O 3 gate oxide on a C-H bonded channel of diamond, high-temperature and high-voltage metal-oxide-semiconductor field-effect transistor (MOSFET) has been realized. From −263°C (10K) to 400°C (673K), the variation of maximum drain-current is within 50% at a given gate bias. The maximum breakdown voltage (V B,max ) of the MOSFET without a field plate is 996V at a gate-drain distance (L GD ) of 9µm. We fabricated some MOSFETs satisfying V B,max /L GD > 200V/µm (2MV/cm). This value is superior to those of lateral SiC or GaN FETs.

18 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202230
202111
202016
201915
20189