Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

A new three-dimensional MOSFET gate-induced drain leakage effect in narrow deep submicron devices

Abstract: A new MOSFET gate-induced drain leakage (GIDL) mechanism is observed in narrow-width trench-isolated MOSFET devices Electrical measurements and device simulation show that this mechanism occurs due to electric-field enhancement at the three-dimensional intersection of the gate-to-drain overlap region and the trench corner The enhanced electric field increases the GIDL current at the 3-D intersection region This imposes another fundamental limit on MOSFET dielectric scaling in deep submicron narrow-width devices Since the 3-D GIDL mechanism is caused by a high electric field, trench corner rounding and lightly doped drain junctions provide effective solutions >

Method of making a depleted poly-silicon edged MOSFET structure

Abstract: A field effect transistor with reduced corner device problems comprises source and drain regions formed in a substrate, a channel region between the source and drain regions, isolation regions in the substrate adjacent the source, channel and drain regions; and a gate having a gate dopant over the channel region and separated therefrom by a gate dielectric. The isolation regions define corner regions of the channel along interfaces between the channel and isolation regions. The gate includes regions depleted of the gate dopant and overlapping at least the channel region and the isolation regions, such that voltage thresholds of the channel corner regions beneath depleted portions of the gate conductor layer are increased compared to regions of the channel between the corner regions. The field effect transistor with reduced dopant concentration on the MOSFET gate "corner" has an improved edge voltage tolerance. The structure has improved edge dielectric breakdown and lower MOSFET gate-induced drain leakage (GIDL). This structure is intended for analog applications, mixed voltage tolerant circuits and electrostatic (ESD) networks.

New approach for the extraction of gate voltage dependent series resistance and channel length reduction in CMOS transistors

Abstract: The resistance based extraction method for the determination of effective channel length and series resistance behaviour with gate bias is critically analysed. The impossibility of extracting the gate voltage variations of these parameters concurrently is demonstrated. Then a new parameter extraction procedure is given and experimentally applied to a wide range of technologies, from 1.2 /spl mu/m down to 0.1 /spl mu/m. Finally, the lack of resolution in the determination of channel length reduction and series resistance when the effective gate bias tends to zero and the impact of the substrate gate bias on these parameters is studied in detail.

Simple theory for threshold-voltage modulation in short-channel m.o.s. transistors

Abstract: The threshold-voltage modulation ΔVr of m.o.s. transistors, due to substrate bias VR, is determined using a simple 2-dimensional approach. It is shown that, for a given substrate bias, the ΔVT of short-channel devices is less than that of long-channel devices. It is also shown that the intrinsic (zero substrate bias) threshold voltage of short-channel devices is less than that of long-channel devices. The functional dependence of ΔVT on VR is derived, and verified experimentally.

Reference current source circuit including added bias voltage generator circuit

Abstract: A MOS transistor generates an output current based on a voltage induced across a drain and a source thereof. A gate bias voltage generator circuit generates a gate bias voltage so as to operate the MOS transistor in a strong-inversion linear region, and applies the gate bias voltage to a gate of the MOS transistor. A drain bias voltage generator circuit generates a drain bias voltage, and applies the drain bias voltage to the drain of the MOS transistor. An added bias voltage generator circuit generates an added bias voltage, which has a predetermined temperature coefficient and includes a predetermined offset voltage, so that the output current becomes constant against temperature changes. The drain bias voltage generator circuit adds the added bias voltage to the drain bias voltage, and applies a voltage of the adding results to the drain of the MOS transistor as the drain bias voltage.