Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

A Study of Parasitic Series Resistance Components in In–Ga–Zn–Oxide (a-IGZO) Thin-Film Transistors

Abstract: We extracted the effective channel length and parasitic series resistance in a-IGZO inverted-staggered etch-stop (ES) TFTs. When there is an overlap between the drain or source electrode and the FET channel, the resistance of the channel underneath the overlapping regions is very low compared with other channel region resistance. As a result, the effective channel length is smaller than the physical length. The aforementioned definition of effective channel length in terms of device geometric parameters seems to be specific for ES a-IGZO TFTs.

A Computational Study of Dopant-Segregated Schottky Barrier MOSFETs

Abstract: A dopant-segregated Schottky barrier MOSFET is simulated by Monte Carlo method in this paper. The feature that dopant-segregated structure can improve on-current is revealed. The influence of dopant-segregated structure parameters on device performance is investigated, and the guideline for device design optimization is that the dopant-segregated region should overlay the whole Schottky barrier region. Some carrier transport details are also demonstrated here. The maximal velocities at source and drain sides all decrease with the increase of dopant-segregated region length. The maximal velocity at source side shows saturation with the existence of dopant-segregated structure when drain voltage increases while the maximal velocity at drain side shows no saturation.

Drain-induced barrier lowering in buried-channel MOSFET's

Abstract: In the literature, it is unclear whether or not buried-channel (BC) MOSFETs are less resistant to drain-induced barrier lowering than surface-channel MOSFETs. The authors clarify this confusion and experimentally demonstrate the relationship between the threshold voltage and channel length reduction for normally-on (inverting) BC-MOSFETs. The results are compared with similar measurements on surface-channel MOSFETs. It is shown that BC-MOSFETs are more prone to drain-induced barrier lowering than surface-channel MOSFETs. A simple analytic model is derived for the subthreshold current in small-geometry BC-MOSFETs. The model shows good agreement with experimental measurements and with subthreshold currents obtained using a two-dimensional numerical simulator. >

10 nm nominal channel length MoS 2 FETs with EOT 2.5 nm and 0.52 mA/µm drain current

Abstract: In this abstract, multi-layer MoS 2 field-effect transistors (FET) [1] with record short 10 nm nominal channel length (L ch ) and ultrathin gate dielectric (EOT∼2.5 nm) have been demonstrated. These aggressively scaled devices show high performances including a drain current of 0.52 mA/µm, an on/off ratio larger than 106 and an extrinsic transconductance of 142 µS/µm. This study sheds light on the impact of channel thickness, channel length and gate dielectric scaling in multi-layer MoS 2 FETs.

Field-effect transistor with structure for suppressing hot-electron effects, and method of fabricating the transistor

Abstract: A polysilicon gate (42) of an N-channel MOSFET (40) includes a P+ doped central portion (42a), and N+ doped lateral portions (42b,42c) which face an N-type source (24c) and drain (26c) respectively. An N-type dopant is implanted into the surface portion of a P-type channel region (18) to reduce the surface doping and adjust the transistor threshold voltage to approximately 0.8 volts. The lowered channel doping reduces the electric field at the drain (26c) and suppresses injection of hot electrons from the drain (26c) into the gate oxide (14), and also reduces the electric field across the gate oxide (14) and suppresses charging thereof by hot electrons. N-type and P-type graded strata (26a,26b) are formed between the drain (26c) and substrate (12) and create two reverse biased diode junctions which block flow of drain current from the channel region (18), thereby eliminating the creation of hot electrons and impact ionization in the bulk portion of the drain diode, and channel charge carriers through the surface portion of the channel region (18). The surface portions of the channel region (18), drain (26c) and graded strata (26a,26b) are shorted together to form a shorting surface channel through which the charge carriers are constrained to flow.