Channel length modulation

About: Channel length modulation is a research topic. Over the lifetime, 1790 publications have been published within this topic receiving 34179 citations.

Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

Abstract: An analytical drain-current compact model for lightly doped short-channel ultrathin-body and box fully depleted silicon-on-insulator MOSFETs with back-gate control is presented. The model includes the effects of drain-induced barrier lowering, channel-length modulation, saturation velocity, mobility degradation, quantum confinement, velocity overshoot, and self-heating. The proposed model has been validated by comparing with the experimental transfer and output characteristics of devices with the channel lengths of 30 and 240 nm and with back bias varying from −3 to +3 V. The good accuracy of the model makes it suitable for implementation in circuit simulation tools.

Semiconductor device having at least two field effect transistors and method of manufacturing the same

Abstract: A complementary field effect transistor with an N channel MOSFET and a P channel MOSFET formed on the same substrate is disclosed. On the P type main surface of the semiconductor substrate, an N channel MOSFET is formed comprising a gate electrode and a pair of impurity regions which becomes a pair of source/drain regions. Each impurity region of the N channel MOSFET comprises an impurity region of relatively low concentration formed so as to extend to beneath the above mentioned gate electrode, and an impurity region having a concentration higher than that of said impurity region having low concentration formed in a position at a distance from said gate electrode joining the impurity region of low concentration. The length of the portion located beneath the above mentioned gate electrode in the surface portion of the impurity region of low concentration is not less than 0.1 μm in the direction identical to the direction of the channel length. This complementary field effect transistor has both reliability and high speed in the N channel MOSFET, and without punch-through in the P channel MOSFET, even though the devices become more minute.

A numerical analysis of avalanche breakdown in short-channel MOSFETs

Abstract: Recently, the electrical characteristics for the short channel MOSFETs (Metal-Oxide-Semiconductor field effect transistor) have become important because of the increasing density of LSIs (Large Scale Integrated Circuits). One of the methods to understand the characteristics of the short channel MOSFETs is the two-dimensional analysis of the MOSFETs, and many studies about threshold voltage and other items have been made by using the two-dimensional method. In this paper, the drain breakdown characteristics for the short channel MOSFETs are calculated by the two-dimensional analysis method. Consequently, one of the phenomena for the short channel MOSFETs, that the breakdown voltage decreases with increase in gate voltage, is reduced to the difference of the electric field strength distribution from that of the long channel MOSFETs. This variation of the electric field distribution is caused by the strong influence of the electric field from the drain upon the considerable region in the substrate of the short channel MOSFETs.

Anomalous punchthrough in ULSI buried-channel MOSFETs

Abstract: It is shown that punchthrough (pt) in very short buried-channel P-MOSFETs cannot be suppressed by diminishing the p-channel thickness t/sub c/. This is because of the drain-induced channel enlargement (DICE) effect, which switches on and becomes the dominant pt mechanism for very short channels. The DICE effect is independent of t/sub c/, and therefore the DICE-related pt component flows even with t/sub c/ to 0, so that strategies other than channel thinning are needed for the pt to be suppressed. A new implant step, called the retrograde implant, together with the LDD (lightly doped drain) structure, is shown to be able to suppress the DICE effect and thereby shift the limit of pt-immune BC-P-MOSFETs from 0.6 mu m down to 0.3 mu m. The pt encountered below a channel length of 0.3 mu m has been found to result from a pure DIBL effect rather than an incomplete DICE effect suppression. As a result, a further gain in channel shortening (without pt) would require the channel to be even thinner than 0.04 mu m. >

p-MOSFET total dose dosimeter

Abstract: A p-MOSFET total dose dosimeter where the gate voltage is proportional to the incident radiation dose. It is configured in an n-WELL of a p-BODY substrate. It is operated in the saturation region which is ensured by connecting the gate to the drain. The n-well is connected to zero bias. Current flow from source to drain, rather than from peripheral leakage, is ensured by configuring the device as an edgeless MOSFET where the source completely surrounds the drain. The drain junction is the only junction not connected to zero bias. The MOSFET is connected as part of the feedback loop of an operational amplifier. The operational amplifier holds the drain current fixed at a level which minimizes temperature dependence and also fixes the drain voltage. The sensitivity to radiation is made maximum by operating the MOSFET in the OFF state during radiation soak.