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Chip

About: Chip is a(n) research topic. Over the lifetime, 44555 publication(s) have been published within this topic receiving 352381 citation(s).


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Patent
15 Oct 1987
Abstract: A multiple access, spread spectrum communication system and method for providing high capacity communications to, from, or between a plurality of system users, using code-division-spread-spectrum communication signals. The communication system uses means for providing marginal isolation between user communication signals. The marginal isolation is provided by generating simultaneous multiple steerable beams; using an omni-directional antenna with polarization enhancement; using power control devices to adjust the output power for user generated communication signals either in response to their input activity level, or in accordance with a minimum allowable power for maintaining a communication link. The communication system can also employ a means for transmitting a predetermined pilot chip sequence contiguous with the code-division-spread-spectrum communication signals. In further embodiments the communication system employs a plurality of user terminals linked to each other or to other services through one or more terrestrial or satellite repeaters. Multiple satellite repeaters are operable in a new communication mode to obtain further gains in signal isolation.

1,218 citations

Journal ArticleDOI
TL;DR: It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.
Abstract: With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.

1,093 citations

Journal ArticleDOI
TL;DR: The receiver adapts to the actual jammer-to-signal(J/S)ratio which is critical when the level of interference is not known a priori, and optimizes the code rate and minimizes the delay required to decode a given packet.
Abstract: It is well known that if the data rate is chosen below the available channel capacity, error-free communication is possible. Furthermore, numerous practical error-correction coding techniques exist which can be chosen to meet the user's reliability constraints. However, a basic problem in designing a reliable digital communication system is still the choice of the actual code rate. While the popular rate-1/2 code rate is a reasonable, but not optimum, choice for additive Gaussian noise channels, its selection is far from optimum for channels where a high percentage of the transmitted bits are destroyed by interference. Code combining represents a technique of matching the code rate to the prevailing channel conditions. Information is transmitted in packet formats which are encoded with a relatively high-rate code, e.g., rate 1/2, which can be repeated to Obtain reliable communications when the redundancy in a rate-1/2 code is not sufficient to overcome the channel interference. The receiver combines noisy packets (code combining) to obtain a packet with a code rate which is low enough such that reliable communication is possible even for channels with extremely high error rates. By combining the minimum number of packets needed to overcome the channel conditions, the receiver optimizes the code rate and minimizes the delay required to decode a given packet. Thus, the receiver adapts to the actual jammer-to-signal (J/S) ratio which is critical when the level of interference J is not known a priori.

1,073 citations

Journal ArticleDOI
Abstract: An analysis of the chip geometry and the force system found in the case of orthogonal cutting accompanied by a type 2 chip has yielded a collection of useful equations which make possible the study of actual machining operations in terms of basic mechanical quantities. The shearing strain undergone by the metal during chip formation, and the velocities of shear and of chip flow are among the geometrical quantities which can be quantitatively determined. The force relationships permit calculation of such quantities as the various significant force components, stresses, the coefficient of friction between chip and cutting tool, and the work done in shearing the metal and in overcoming friction on the tool face. The experimental methods by which such analyses can be readily made are described. Observed and calculated values from typical tests are presented.

1,039 citations

Journal ArticleDOI
01 May 2001
TL;DR: This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design.
Abstract: Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

1,030 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20227
2021528
20201,490
20192,119
20182,253
20172,328